Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Will multi-voltage techinque be applied within a single combinational block in the circuits? In other words, does one combinational block(between two flip-flop) has only one voltage level supply( within the same voltage island) ?
As known to me, there are only three big EDA tools' providers: Synopsys, Cadence and Mento Graphics. I am very interested whether there will be more job opportunities offerred by other companies?
I am a Ph.D. student in EDA algorithms especially in timing analysis field in China. Should I...
thanks for your message,
*****************************************
1. "tlihu": the first item you mentioned is really hot in my view. it relats with mixed-signal design and simulation which is also the main research area I am interested in (of course, EDA for this area). The second is common...
I am a master student who want to go on my Ph.D. study on Analog EDA. Most research experiences of me are related with vlsi physical design, so are there some papers giving the general description of this field with emphasis on latest development and trend?
It will surely be necessary for a...
by the way, the design I mention have one hard IP embeded, but the IP is provided by another company according to the foundry's 3M technology, so we could only do LVS without that hard ip before do runset.
oh, i have recently also faced with this problem. I have gotten contact with the foundry and they transferred me with a updated package (in fact, it is a lvs runset file) and let me to run it with Herculus(Synopsys) after GDSII out from Apollo. I think it may additionally cause some errors by...
recent I designed a PCI target chip with interface to 93c46(off the chip). But I am not clear how to evaluate the design. More general, what's the most needed feature for a serial I/O chip (or IP) design, such as SCI/SPI or mentioned above?
I am now do a SAR ADC design and need to do mixed-signal simulation on my design.
The digital part of the circuit is descripted with VerilogHDL at RTL level. And then I make it as a symbol and integrated into a schemetic with analog part. The stimulus to digital part is descripted with...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
