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Recent content by honey

  1. H

    FPGA(Xilinx) IP Cores needed!

    me too ,could you give me a copy
  2. H

    VHDL vs Verilog which more popular?

    different continent different prefer
  3. H

    iverilog / starters tutorial in verilog design / synthesis

    i-verilog use google to search ,there are many tutorial about verilog
  4. H

    charge pump design - please help

    Increasing the BW to reduce the total noise power of the synthesizer is a possible way to go. There is an optimum. That is where the normally flat noise of the multiplied reference intersect the 1/f of the VCO. In the between the PN gets bumpie. From the phase margin standpoint 1/10 is not the...
  5. H

    look at my vhdl, why it doesn't work after synthesis

    please check your synthesis constraint script first. because if you make wrong constraints, the synthesizer will produce false result. always remember, it's the designer, not synthesizer, who is responsable of the correctness of the design.great
  6. H

    Analog IC design in Windows environment

    use cadence ic in linux will be good
  7. H

    problem about synopsys synthesis

    inside your always block. example: cell (.Z(wire1), .A(VCC)); always ..... if (rst) reg1 <= 1'b0; else reg1 <= wire1;
  8. H

    Is anyone here using ModelSim5.6a ?

    license too troublesome
  9. H

    analog behavioural modeling

    behavior modeling , is not exact,
  10. H

    Things about SmartSpice, Hspice...

    how to compare
  11. H

    IsSpice vs. saber designer

    smps simulation isspice who has ispice, share ok?
  12. H

    What about L-Edit/SDL Tools?

    no , it can only do schematic
  13. H

    MENTOR WG2000.5 and WG2002 Installation Problem on XP

    why so many people want use winxp
  14. H

    Saber/Modelsim licensing problem

    may be changle the flexm server
  15. H

    how to link from ISE5.1 to its modelsimXEII

    THIS IS SIMPLE U CAN FIND THE ANSWER IN THE HELP DOCUMENT
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