Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by HolySaint

  1. HolySaint

    ASIC Desgin Flow Chart - RTL to GDS

  2. HolySaint

    wanted! ICC 200703 lab guide

    btw,who can give a link about dc lab and lab guide here?
  3. HolySaint

    wanted! ICC 200703 lab guide

    wang yi de you xiang a haha
  4. HolySaint

    syn problem about bus

    thank you. i am clear now. regards
  5. HolySaint

    syn problem about bus

    module u(d1,clk,rst,d2); input clk,rst; input [7:0] d1; output [15:0] d2; wire [7:0] mark_a; u1 u1(mark_a,clk,rst,d1); u2 u2(mark_a,clk,rst,d2); endmodule // sub module module u1(a,clk,rst,d1); input clk,rst; input [7:0] d1; output [7:0] a; reg [7:0] a; reg [15:0] re; wire...
  6. HolySaint

    syn problem about bus

    a si timing_delt, i forgot to say a is an output reg re is just a reg reg [15] re; wire [7] df = re[15]? 8'h81:8'h7f; always . a<=((re[15]&~(&re[14]))|(~re[15]&(|re[14])))?df:re[7]; ............... and there is submodule use like this fa fa1(...,...,a); so , i think there is no replace wire...
  7. HolySaint

    syn problem about bus

    the log said nothing always @(posedge clk or ...) ... a <= 。。。 i will check the value agian the mismatch is found by ncsim Added after 14 minutes: i use flatten compile Added after 15 minutes:
  8. HolySaint

    syn problem about bus

    thank you, i found that the a[7] is also used in other submodule and b[7] is always behigh,but other submodule use a[7],so i think the syn tool should not remove the wire. Added after 6 minutes: and a is an output port in this module,it input to other module
  9. HolySaint

    syn problem about bus

    the missed net connected nothing, i will chenk my rtl again thank U but when i sim the rtl,the two nets connect normal. the rslt is right Added after 12 minutes: i use this parameter num=7; always... .... b<=a[num]?a:-a; .... does this take the error? i will try syn again.
  10. HolySaint

    syn problem about bus

    i have a 8 bits bus a when i syn the rtl,i found the bus a is define like this wire [7:0] a; but where the pin connect to a[0] and a[7] connected other wire, and there is no use of this two bits. what happened? regards!
  11. HolySaint

    [ICC]DC to MW translation failed - no CEL view open

    when i read in my sdc generated by dc,it takes this warning,and the clock was not generated. my sdc version is 1.5 icc 200906sp3 who can give a reslution? regards!
  12. HolySaint

    The tool has just encountered a fatal error:

    I don't have the account of solvnet. orz
  13. HolySaint

    The tool has just encountered a fatal error:

    I often met this when i use icc. I'm sure there is no error in my script. Server: Xeon 5530,8Gmem I want to know how can i fix this? thanks! The tool has just encountered a fatal error: If you encountered this fatal error when using the most recent Synopsys release, submit this stack trace...
  14. HolySaint

    Dual Port ram Simulation Issue

    I do like shethpurak,but when i sim the netlist syn by dc,read happens at the same time I get the rd_en. I use "<=" .
  15. HolySaint

    Hi ,help for tsmc 0.18 cmos tluplus

    U should generate by yourself.
See more

Part and Inventory Search

Back
Top