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This seems like the most likely cause. I found Altium generates a separate file for the slotted holes, although I am not sure what I did differently to make it do this. So, hopefully now it works. I am about to send the files for manufacture. We'll see!
Greetings,
My PCB has a USB connector that has two holes that go to the USB shield and help keep the connector firmly connected to the PCB. But when it arrived, I found that they had filled these holes! So I had to clip off those legs to solder it, and just solder them to these sort of pads that...
Greetings,
Background/Context/Goal:
My goal is to open a simple UART session, be it in Putty or any other software, so I can see print statements (from the FPGA to the PC) for debugging my programs on the FPGA.
I am testing this with the "Hello World" sample application in Xilinx SDK
I am using...
Greetings,
I am trying to figure out the overall gain of this circuit analytically. Simulations and experiments both show that it is 0.0832, but how do I go about calculating this by hand? I would greatly appreciate any help!
After some messing around with the code I found a solution. Unfortunately there are timing errors with my implementation, but it removed the error I was struggling with. My solution was to change the values inside of the lookup table by dividing each by 1000. So I hard-coded those decimal...
Greetings,
I am using a sinewave lookup table to generate an SPWM signal. I am adding a soft-start feature where the modulation index starts at 0, then after after 10 seconds it starts to gradually increase to 0.1 over 20 seconds. The problem is it does not like having a variable real number...
Greetings,
I am trying to generate a bitstream, but it is telling me there is a combinatorial loop occurring with pwm1N, pwm2N, and pwm3N. It does not say where/how/why this happens in the code, so I am at a loss for how to fix this. Is there someone who could help me identify where/how it is...
Thank you for the helpful reply! Like you said, I had to change it to trigger the deadtime timers in the clk's posedge. Had to sleep on it, but today I thought up a way of doing it. Now it generates the bitstream successfully.
Hello,
I implemented a program that outputs SPWM signals with deadtime. The deadtime works like this:
On every negative edge of 1P, set deadtimer1N = deadtime
On every positive clk edge, if deadtimer1N != 0 then set deadtimer1N = deadtimer1N - 1
This works perfectly in simulation, as I show...
Hello Barry,
Thank you, yes it was not liking me comparing reg to integer. It was also having some problems when counter reached below 0. I changed everything to integer, and also shifted everything to stick to positive values, and it finally works. Thank you for your help!
Hello,
I have written code to generate a simple triangle wave that varies from -1250 to 1250 (-MAX to +MAX). I used MATLAB to verify that the logic itself works for generating a triangle wave, by copy/pasting the code into MATLAB and making minor syntax changes so it would work in that...
Thank you for your helpful response! Would addr simply be initialized like this?
reg addr;
How would I use this? Do I just set addr to every value from 0 to 49 and then I can call sine[x], with x being some number from 0 to 49?
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