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Hi all, I am designing a comparator, the one input is dc voltage(ref voltage), and the other is square wave, what's worse, the low voltage of the square wave is varying. My problem is : how can I get a constant duty cycle output when the low voltage of the square wave is varying. Thanks for reply!
To Itrlspree: IIP1db from the result of the PSS is -19dBm. In your reply, I get that S parameter may be not valid when the input power higher than (IIP1db-10dBm). And my question is that if I use PSP to simulate the S parameter, can I trust the result from the PSP, when the input power hiher...
To BigBoss: The input impendence in my design is 50 ohms. Thanks.
To jiripolivka: The simulation is the guide of the circuit design, and I think we cannot skip it when we design a shematic. Usually, we should adjust the parameter of the shematic according to the result of the simultaion. You...
Thanks jiripolivka for reply.
However the reply does little help for me. What I want to know is that why the result of the PSS does not match the result of the SP or PSP. The result of the SP shows that the input is matched when the power of the input ranges from -40dBm to 0 dBm, while the...
I am designing a narrow band LNA, the range of the input frequency is from 1G to 1.05GHz. And I have used SP in spectre to simulate the input match. The S11 has been reached -10dBm from 1G to 1.05GHz, wihch means the input match is ok(in my mind). After this, I used PSS in spectre to simulate...
Hi, dick_freebird
In your first reply , I get that the leakage current is more important to phase noise than dc current mismatch. In your second reply, I get that the leakage current is not that important to phase noise compared with pump set current. So, why we should consider dc current...
Hi，dick_freebird
In your reply， I get that current glitch is more important to phase noise than dc current mismatch, could your please tell me why. And if this is right, we can choose a low w/l of switch to get low current glitch, ignore the high vds of switch and high dc current mismatch...
If the w/l is small, when the current is high (>100u), the Vds of the switch will be very high, it will force the MP2 or MN2 into triode at high voltage or low voltage of Voutcp. This will make the dc current mismatch high. However if we select the high w/l to make the mismatch low, the glitch...
I am designing a charge pump for PLL.
The structure is similar to traditional one which is: cascode pmos as up current, cascode nmos as down current, the middle is switch. The output voltage is from 0.4V to 1.4V as VDD=1.8V. If I want to get the DC current mismatch( (Iup-Idn)/[(Iup+Idn)/2])...
pll settling time
First I should thanks for your reply, AdvaRes and biff44.
I have got AdvaRes`s suggestion, you think that the initial frequency difference is small, so the small signal model can work here. But if I cannot use a big Icp and what`s worse, the bandwidth is small than 50 khz...
pll settling time
Thanks tor AdvaRes`s reply.
However, it seems that you have not got my problem. My problem is that: at the start, as from frequency difference, pll should charge or discharge, but as from phase difference, pll has to discharge or charge. These two situtaiton is opposite. What...
Hi, everybody,
A problem encountered when I use tsmc18rf process to design divider by 2. When I use normal device, the schematic can easily work to 3GHz, but if I use rf device, I should consume much more current to reach 3GHz. My problem is that what is the work range the normal device in...
pll settling time
Thanks for the reply.
AdvaRes`s suggestion is simply swapping ref signal and the feedback signal, however at the start of the pll, we do not know what is the situation. Maybe we need not swap the two signal or we need swap the two signal. If we use this suggetion, how can we...
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