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Thanks for that!
I can further my questions like this:
I wonder if you have some tutorials to guide choosing FPGA chips?
To FPGA, it is more important to know how to choose a suitable FPGA, not too expensive, however, compatible for the logic;
For ASIC, it is more important to achieve the...
Hello, guys,
may i ask 1 naive questions:
1. how do you know the size of a asci or fpga design? when you say size, do you all mean the cell number or something else?
Thanks,
For the second flow, after i generated a ddc file from DC, i can use the ddc to generate DEF/FP files in ICC, then i can use the def and former ddc files as input data into DC (one of Design compiler topographical feature).
To question one, I got answers from experienced engineers that we can adopt different strategies within one power domain, please help with other questions, thanks in advance!
Hi, experts,
I have the following questions, would you please check the questions and see if can resolve?
one : Can multiple retention/level_shifter/isolation strategies set to one power domain?
two ：Have any summaries about the isolation/level_shifter usage scenarios in the design, i know...
Anyone knows? I have a serials of hierarchical modules to deal with, and I need a command (or any report can show the top design?) to get the top design names of these modules.
Thanks in advance!
Eric
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