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I feel checking for no timing issues is not really the best way. As there could be no timing issues after route_opt or signoff as well. anything specific that is done during chip finish that i can check in the cel? like insertion of specific antenna or something???
Thanks so much. Doping concentration was wat i was looking for.[COLOR="Silver"]
What would be the unit for Process(doping concentration) ?? or is it 1.3 times something?
1) Suppose we have a PVT corner with 1.3/1.08/130 . what does that number 1.3 really denote.
2) Also can this happen that 2 scenarios in the design whose PVT corner numbers differ only by Process.
Like sc1 = 1.3/1.08/130 and sc2= 0.7/1.08/130.
Thanks
Thanks.
Consider a scenario where there are ILMs in the block. RC scaling is done for signoff stage at the top level. Will this cause any errors in power calculation??
I am using Synopsys IC compiler and commited hierarchy at design planning stage. Now I did Block level implementation for those soft macros and have the CEL views fr them. At top level how do i link the references correctly.
PS- I am trying to compare runtime and Memory usage with and without...
How can I display design related information for the current design without using the actual command "report_design_physical". Any ideas will be appreiciated
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