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STA is not must in pre-layout stage, it's used in post layout for timing signoff. STA is static timing check, so we need post simulation for check dynamic timing, such as asyn logic.
icg clock gating
Another way use the following logic, it will glitch free.
always @ (negdege clk or negedge rst) begin
if (~rst) begin
en_reg1<=1;
en_reg2<=1;
end
else begin
en_reg1 <= en;
en_reg2 <= en_reg1;
end
end
clk_gate = clk & en_reg1;
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