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Recent content by herwis

  1. H

    implement counter using 16V8 !!!

    Thanks guys, I need just to draw the implementations on the avantis 16v8 diagram. i don't need the vhdl code. the requirement is to implement the up/down counter, say 2 bit up/down counter with clear(i guess i can use PTD as a clear) and enable??? and it should be open drain output. again I need...
  2. H

    implement counter using 16V8 !!!

    thank u so much, but im kind of confused. could u give me more info about implementing the counter on 16v8 with clear and enable.
  3. H

    implement counter using 16V8 !!!

    thanks. i appreciate.
  4. H

    implement counter using 16V8 !!!

    Hi everyone , I need to implement up-down counter with synchronous clear, enable and open-drain output by using 16V8 chip. any help is appreciated because im new in this field. thanks
  5. H

    how do you make an open drain output on a 16v8 fpga?

    Thank u so much for ur reply, but the problem im new in this field, so could u give me more information and why it's available only in complex mode?
  6. H

    how do you make an open drain output on a 16v8 fpga?

    Hi, how do you make an open drain output on a 16v8 pld? Thanks
  7. H

    testbench simulation using modelsim.

    Thanks alot, now i got rid of the errors, but the problem it gives me "U" in the output!!!!
  8. H

    testbench simulation using modelsim.

    Hi, I am trying to simulate a program using testbench on modelsim, but every time it gives me this error on modelsim: # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). # Time: 0 ps Iteration: 0 Instance: /testhw7/u1/u3/rom1 # ** Warning...
  9. H

    vhdl code help needed????

    Hi I have a vhdl code counter that counts in binary from 6 to 88 then it rolls over to count down from 88 to 6. Now i want to do the same counter but instead of counting in binary i need it to count in BCD. can i show the count values in quartus in bcd? if not please any help how can i do that...
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