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Hi,
You are facing problems with your layout design.
DRC- Design Check Rule .
So, there are issues with your design..You haven't placed the gates well.
Also, Keep in mind the lambda rules while making layouts.
A inverter in Microwind should look something like this :
Actually, I have to design this circuit.
This is the Analog counterpart of a metastable latch.
So, there's a negative amplifier...I want to design that using CMOS in Tanner (S-EDIT).
This isnt useful, because I have to draw a schematic in S-EDIT. I know the theory well.
But while implementing , I am facing a lot of issues. I am using the ***** version of Tanner.
Re: Need Hspice code for SRAM
I did this in My UG Course. Made a layout for SRAM in microwind. Extracted the Spice netlist using Advanced BSIM4models.
Pasted the same netlist for HSPICE.
And I had satisfactory results.
My SRAM code which was extracted using Advanced BSIM4 Models:
CIRCUIT...
How to make the latch metastable in S-Edit (Tanner tools) ?
I have tried a lot of times..but failed each time . I used the "setup and hold time violation method".
Can someone demonstrate the same in S-EDIT.
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