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Yes, I am using HVSON lead-free package and the downbond is about 0.8nH actually.
Because this single-ended LNA is really large-area (Yes, differential arch doesn't suffer from the bondwire problem because of the virtual ground but I can't use it in this design.), I found it is really hard to...
I don't know the details of your active part, if it is LNA from 1.5GHz to 2.5GHz, you could try:
1. Try to use a multi-section matching network, you can use the ADS to design and optimize it.
2. Try to use the transformer feedback, or resistive feedback.
3. Try to use lossy matching network...
Hi all,
Currently I am designing an LNA around 2GHz, and I want to use a bondwire inductor about 0.2nH as the emitter degeneration part. Is it possible to realize it by multi bondwires in parallel? I need it to make a fast estimation, any suggestion is appreciated.
For the simulators, HFSS...
Hi,
Currently I am using a large-area SiGe transistor to design a LNA chip, the bias current can be as large as 50mA. The emitter of the transistor is connected to the ground directly to provide a input matching and a good noise figure at the same time. (It is a large-area devices, so it is...
Hello, everyone,
Currently I am designing an single-ended LNA, I have used PSS+PAC and got the IP3, but how to draw the plot of IP3 versus bias current (or other variables) in spectre? Thank you very much for helping a noob...
Best regards,
hbsustc
Yes, you are right. Real time delay of LE buffers can't be got from timing simulation, normally it is smaller than the simulated value. So I need to program the chip and measure it. Thank you!
Thank you for your suggestions, FvM, I'm afraid its performance will be deteriorated by the following points:
1. For the Logic-cell delay line, its delay is not accurate, it will be influenced by power-supply and temperature.
2. The 3-stages ring oscillator realized in FPGA seems not feasible...
phase delay clock
Hello, everyone. I have an old Atera FPGA, there isn't any PLL on it. Now I have a reference clock about 10MHz, the problem is how to generate another reference clock whose phase leads the former by 45 degrees, or lags the former by 45 degrees? It seems I have to use code to...
Ubuntu 6.06 LTS is a well-suited version to run EDA tools especially for the laptops, Cadence IC5141 (5033), ADS2008, Modelsim, Cosmos work well on it.
Hello, everyone. I met one problem about symmetric microstrip inductor as the attachment, but I don't know how to draw its layout in ADS, can anybody give me a hint about this layout? Thank you very much in advance.
multiplier
Hi, I want to design one Baugh-Wooley pipelined array multiplier as this figure. I have completed the part of FA with and gate now, but I don't know how to realize the latch part for the partial products.
I mean, if I want to use "generate" statement, how to write the code so it...
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