Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi cyboman
I asked onw who is working on modelsim QA to get the answer I sent before. However, according to my understanding, connectivity mentioned means connectivity between instantiated components, Checking port widths, checking port existence and so on ...
I am also interested in this, does elaboration time is after or before compilation time. I think it is after compile time. Is this the time when compiler directives are checked ??
Anyone from USA/Canada/Europe interested to start a VLSI design center in a low cost region in Middle-East, Kindly contact me. I can be your contact person and I know how to hunt needed resources
As I got a notification to send the final solution from admins
here you are
2 solutions
1- use readmemb, readmemh for read binary and hex data. This option is supported in most of tools
2- use PLI (standard file IO functions) like scanf..it is more powerful and gives more flexibility but not...
Hi Gents
I have a text file that is containing stimulus data pattern. I need to read this file using a verilog task to apply data pattern sequence to my DUT.
Could any-one help me in this. I have very limited time to do this
Regards
Haytham
Re: Free tool like modelsim
Thanks
I want ot ask are these tools are close to modelsim ??
also I want to ask if xilinx web-back is good or not compared to these
Regards
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
