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hi everyone
what is the input current of the spartan 3e starter kit. because i will give the external input to the user header so i do not know how the maximum current we give to the spartan 3e kit pls give the rply
hi all
pls i need help in lcd interfacing i develop one code for 8 bit counter when it will be start pin is high then counter is start and when start pin is low then counter is zero last output of count will display to lcd in spartan 3e .
so any code for lcd interface that pls help me.
thanks for given a replay
i have tried some lcd code it input is 8 bit so i will directly connect my output of counter to the input of lcd input but it not works.
you says that i convert the that 8 bit into decimal form so any code of lcd in verilog which help me
pls give the rply for that.
hi all
i am working one project i have develop one code for counter when i give the input to the start high then counter will start and when down there input low then particular count output is given this output i display in LCD in spartan 3e kit so pls any idea about how to display bit in lcd.
hi
i am working in spartan 3e project i have the external hardware for temperature measurement so it give the output into the voltage i will connect that output into the spartan 3e kit to analog to digital converter and also my external hardware voltage is +5 to -5 v in spartan 3e ADC maximum...
HI all,
dis is d code for simple 4 bit multiplication.
der is no syntax error in dis program.
but the result is not shown.
i mean result is not proper.
so pls correct code nd replay me.
thanx...
module div(sum,B,Q,A,clock,start,e);'
output [4:0] sum;
reg [4:0] sum;
input [4:0] Q,B;
reg [5:0] T...
hi all
this is my code of verilog hdl. there is some problem in my code that i will give the output of counter in the input of adder but it not connected so any one who tell me that what wrong with my code rply fast.
module top(Reset, clock, Load, Enable, up_down, Q, a, b, cin, summ, carry)...
error-For statement is only supported when the stop test condition is a comparison between the loop variable and a constant.
any one know how i solve that.
module top(n, result);
input [3:0] n;
output [31:0] result;
reg [31:0] result;
always @(n)
begin
result=factorial(n);
end
function...
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