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Dynamic Simulation
There are two methods used for verifying a design against a standard.
1. Formal verification or equivalence testing uses a tool, such as Synopsys Formality, to test the design in one form such as the RTL description which is known to be functionally valid against a second...
Thanks rjainv.
I find the PLI interface very cumbersome and inefficient - I've started researching some of the more recent tools and hope to find something easier to integrate.
We will need to prepare processor code in C, compile and simulate the execution to verify the function.
I have a need to update a legacy verilog verification environment. The ASIC is entirely in verilog, but will be integrating a processor and this will require the inclusion of a C/C++ interface. There are a number of tools in use and I am in the early stages of evaluating what approach to take...
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