Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hi i'm designing a neural amplifier and i have got the required results but it has a 30 mv glitch i need to remove it with a simple circuit what should i do ? i attached the required schematic and an image of the output .thanks in advance.
output waveform :
tgate switch that has this glitch...
i altered my previous block diagrams to the one i attached and i got some output results that i don't know if its alright or not ! in the output waveform of my reference paper output stays zero for 7 rising edge of clock pulse and then it gets changed . for my design it changes after 2 . can...
i figured out how to implement shift register stage and ROM stage. but I'm stock at the tree shift adder stage . I implemented it from a block diagram from some other paper(i attached it ) and i attached my implementation too.
i have the following problems : 1-n stocks in 1 value and never...
that's not the block diagram i meant ! i attached the block diagram that i meant here and the ROM address table too please don't delete them .
and i should ask a question about it to make it more clear :
our input is 8 bits but ROM address is 4 bits how should i connect them ?
**broken link...
thanks . i didn't attached the paper because some times ago one of managers of forum told me that i shouldn't do it and that i should only provide the IEEE link . i attached some pics of the paper .can you tell me what is in the block diagrams ?
hi i am trying to implement a fir filter that is in the paper that i attached its link below with vhdl . the problem is i cant find out what is inside the block diagrams in Figure3 .from section 3 in the paper it seems that we should use a state machine but i have some questions .
1- what is...
Re: how i should design a reset pulse generator in a neural amplifier ?
according to the paper input frequency is constant . when reset pulse generator is operating it makes the amplitude lower and the output voltage is folding.
how i should design a reset pulse generator in a neural amplifier ?
i am designing a neural amplifier from a paper.it make the bits lower by lowering amplitude for optimization in a/d. i uploaded a picture that shows the general circuit .it has an ota and 2 comparator an or and reset pulse...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
