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I am simulating a LC oscillator using HSPICE in Linux and wish to have the phase noise results. But i get the following error while running the simulation. Please help out as its very important. Thanks.
Error: (CNTFET05w.sp:1) hnw error #: sequence error
Error...
I am designing a 60 GHz LC VCO and connecting it with a static frequency divider (SFD).
Both components are working properly independently. The VCO has a CS buffer at the output.
But when i connect them together the amplitude of the VCO buffer output reduced considerably and cannot drive the...
Dear all,
I remove the tank from a cross-coupled topology and see the simulated real part of the impedance seen from the cross-coupled pair. As expected, it has a negative value.
Then i run a sweep by changing the # of fingers of the transistor but the results are opposite to what is expected...
Thanks for your reply FvM. Can you please suggest the solutions to fix the two issues you pointed out?
Also is there a tool which could do the impedance calculation for such a circuit ?
output impedance calculation
I wish to calculate the impedance at the output side of the attached circuit. As an antenna is to be connected with the same impedance at the output therefore an exact value would be needed.
The aim of this circuit is to detect the mobile communication during...
I am simulating a charge pump in C65nm. Icp is 500 uA. The schematic and resulting waveforms are attached.
The questions i have:
1. The up and down currents are not equal, the charging current reaches close to the max current (~484uA) but the discharging current only reaches (~170uA). What...
satellite dish health
Are there any health hazards/precautions involved if a satellite dish is placed inside the house, lets say close to the living room window?
Regards
I am designing a CMOS PLL IC using cadence. The PLL, as we all know, consists of a VCO, a high frequency first divider stage, a series of low frequency dividers followed by a PFD etc.
My question is about the interfacing of the VCO with the first divider stage and
the subsequent divider...
I think you can run a S-parameter simulation and use an expression to calculate the Y-parameters. The real part of this would be the Ron of the switch.
Regards
Referring to Keliu Shu book on CMOS PLL synthesizers, Eq. Nr. 3.7 gives the PLL loop gain as K= (Kpd Kvco R1) / N
where Kpd is the PFD gain
Kvco is the VCO gain
R1 is part of the 2nd order loop filter
and N is the divide ratio
My question is which value of N should be used in this equation...
phase noise and multipliers
You have to chose the Multiplier outputs as oscillator nodes in the PSS simulation. This is because in the next calculation of the phase noise, it will take the calculated carrier frequency from the PSS (in this case multiplier output) and find the phase noise around...
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