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Too bad. I'm writing this code as a part of a bachelors thesis, which I need to submit it in the next 2 days :/ . rewriting such a huge code would be simply crazy. So I will have to work around it somehow. By the way, is there any way to build an interpolator in verilog, which would multiply the...
I see. Well according to Hagenauer's paper, components between fs/128 and fs/64 do not contribute to aliasing so it should be ok if say 50kHz was to pass through right ? What's puzzling me is that the amplitude of the 50kHz signal is only being attenuated by a factor of 2. ( square input with...
Thanks a lot for the help. I used your parameters, now the reponse to a constant input at 10 ist actually 10 but switches to 9 for a short period. I'm not sure how critical this is. I know the code is not synthesizable, so far I've only used the Modelsim compiler, and it worked normally. I...
Hey FvM,
thanks for the reply. I just checked the original code of Meyer-Baese and tested it. However the response to a constant 1 ist between 4 and 3. I expected it to be 1 also.
On a different note, the cic.exe program provided by the author is supposed to calculate the amount of bits which...
Hello neighbor (Aachen here ;)),
well that's good to know. So far I've used 64 and 32 as decimation factors, so what you are saying applies. However, I relied on the code of MAYER-BAESE (DSP with FPGA), and simply modified the decimation factor , the differential delay from 2 to 1 and adjusted...
Hello,
I'm trying to calculate the gain of a CIC decimation filter after bit pruning. I believe bit pruning affects the gain because it is not possible to represent the factor (RM)^N with the limited output precision.
Any help will be appreciated
Hi,
I'm designing a CIC filter on an FPGA. I applied the bit pruning algorithm as described in Hagenauer's paper, however it is unclear to me how the gain is affected by such procedure. Normally CIC filters' gain is (RM)^N. However, after truncation the amplitudes cannot reach (RM)^N due to...
true. I tested it and you are right. The thing that puzzles me though, if I can declare inputs as unsigned in the module but signed in the testbench, or if I have to declare them as signed inputs in both.
Hello,
I'm trying to implement an FIR filter in Verilog and was wondering, if there's any practical way to truncate/round the MAC outputs in order to get the same output bit length as the input. I would simply round the output of the filter to the nearest quantization level, but maybe someone...
Hi,
I am looking for a way to force verilog to use 2's complement arithmetic. I'm not sure if it does it automatically. I heard somewhere that declaring the inputs as 'signed' would do the job. Can someone help me out?
OK let's see here is my code now:
// cic decimation filter : R=64, M=1, N=3
module cicdecim64 (x_in,y_out,clk,reset);
input clk,reset;
input [7:0] x_in;
output [7:0] y_out;
parameter hold=0, sample=1;
reg state; //sample or hold states
reg [5:0] count; //count till 63...
I'm still struggling to get it to work. I only get the 1st output sample because of the initial values. However once the first positive clock edge occurs, the state of i0 changes to x and with it everything else. I tried changing the clock frequency but that did not help.
Yes, that makes sense. I tried inserting the following after the declaration of ports and wires:
always @(posedge reset)
begin
i0<=24'd0;
i1<=19'd0;
i2<=14'd0;
end
while setting reset to jump from 0 to 1 at the beginning of the simulation. However, the compiler returns the following error:
-...
Thanks for the replies. I managed to get it to work. It was a Modelsim problem, it was detecting my code as VHDL. Anyway, I'm facing another problem now. After running the test, the simulation does not get past i0 . Here is my code:
module cicdecim64 (x_in,y_out,clk);
input clk;
input...
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