Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
My question is:
Because Cvin(C7) should be shorted to GND, the Vin should be close to 0 in the beginning.
The Z-diode shouldn't be a major cause this result.(Maybe I'm wrong)
treez
Thank you for your explanation and calculation!!
Yes!!
If Vo=20V,Io=1A.
Can it work??
the Aux side(5-6):
If Vaux=30,Iaux=10mA.Duty=50%.
Can it work??
I just want to ask the definition of 15V@3A &15V@20mA.
Is it absolute or average??
FvM
Sorry, it's my false that I didn't check the files.
This is a new files I have checked.
the LM5021 model has only just 7 pins.
I will simulated in TINA-TI again.
If I have any information or solution, I will reply here.
In order to simulate optocoupler, I use Diodes and behavioral current...
Basically,it can work.
But I discover that the value of Vin is digger than 36(typ Vin ESD) in the beginning.
Theoretically, Vin should be clamped between 30~40.
It is impossible that Vin>40.
Is it a error of LTspice???
plz help me with this problem.m(_ _)m
Hi,
It’s the first time that I design a flyback converter.
I want to ask a stupid question.
Is the value of 15V@20mA/15V@3A Absolute Maximum Rating???
If it is "Absolute Maximum Rating",then the transformer can't operate normally when Vin>90v
EX:
Vin(1-4)=400V
(1-4):(5-6)=6:1
Vaux(5-6)=66.67V...
1.change NMOS for ideal switch
the trend of curve doesn't change.
2.change right side PMOS for ideal current source
the curve have some variation as shown below.
but the current of gate isn't costant in plateau region(Qgd region)
3.from above step,change left side PMOS for ideal current...
In order to measure the gate-source charge and the gate-drain charge of N-channel DMOS(we don't have datasheet and spice model).
Before I actually measure it,I want to simulate the BSS159N_L1 as practice in LTspice.
PMOS is used to imitate the current source.
logic level NMOS is used to imitate...
IXYS only provide Pspice model
because Pspice has Node Limit (75 Nodes)
so I want to use LTspice
then I create a new symbol of IXTT20N50D(NMOS)
but!!
the model doesn't have node as shown below??
*******************************************************
* PSpice Model Editor - Version 10.0.0
*$...
figure as shown below
I want to use bandgap in DC/DC controller
before normal operation,the reference voltage have to be provided first
the common VDD maybe: VDD+-10% or 3~12V
but the commercial product has very large range of Vin
ex:LT8300 Vin:6~100V
have any circuit provide bandgap's VDD...
It's my first time to lay out the PCB
I have a problem as shown below
the right point and the left point can't connect together
the left is a Header, 16-Pin
plz help me with this problem.m(_ _)m
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
