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Recent content by Gunship

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    What does this coding do ?

    What does this do ? If you look at the end of the constant NUMERATOR line, you will see that is has a series of numbers. Those are the value inside the array. For example, NUMERATOR(0) will return a 7, NUMERATOR(1) will return 30, etc. std probably is a std_logic_vector. That is why it needs...
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    [FPGA Xilinx Virtex5] Clock Multiplexing "glitch-free&a

    bufgmux_ctrl Are you sure? I am using a Virtex5 also and I also use BUFGMUX without any problem. I prefer that one because it is simple. If you have a map issue from BUFGMUX, you may have a problem else where. I can probably help you if you post part of the code and the error portion of the map...
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    how to do Image resizing using FPGA

    image scaler bicubic verilog I've seen this topic comes up so many times someone ought to write a tutorial about it. To resize an image takes two processes, resize horizontal and resize vertical. To resize horizontal is easy but resize vertical needs line store. To resize, we use either a...
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    DTMF questions in FPGA

    Goertzel algorithm is a special kind of FFT algorithm that use for DTMF decoding. Here is a quick link about it https://en.wikipedia.org/wiki/Goertzel_algorithm https://ptolemy.eecs.berkeley.edu/papers/96/dtmf_ict/www/node3.html You should also take a look at analog devices ADSP-21XX Signal...
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    implementation of Digital filters in FPGAs

    If you have the money, you can get system generator with simulink. That will allow you to design your filter and genearte the VHDL code for you. But if you don't have any money (like me), you will have to compute the coefficients and implement the filter in vhdl by hand.
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    Help me build an ASYNC ALU

    Re: clockless!!!!!!!!!! Ouch! Why do you want to torture yourself like that? FPGA is NOT designed to do async circuits. Now, that is not to say it is impossible. I've seen some pretty impressive thing others have done. Such as a CPU, which has an ALU inside of course. Here is the link...
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    Need urgent help for Xilinx FPGA!!!

    Mmmm... That is a tough one. Here is what I will do. I am assuming your LVDS does not run that fast and you have series and parallel termination. I will play with the termination to get close to the LVDS level. But watch out for signal integrity issue. I will use either Hyperlynx or Cadence for...
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    what is the best simulater for Analog design?

    I used to enjoy pspice. But that is before Cadence bought it. I prefer the older version that has its own schematic frontend, rather than the OrCad frontend. I crashed it a few times when I model a transmission line with RLC elements. I used to use multisim too. But that was almost 10 years...
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    What do 'If-Else' statements synthesize to?

    In VHDL, if-then-else produces a piority encoder. The case statement produces a simple mux. Gunship
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    Share price forecasting using neural network

    I've done some work in this area during my post grad study. There are two problems I can see with neural network. 1. The number of nodes you will need is up to you. But more nodes means more computation is required. They do go up substantially if you fully implemented the entire neural network...
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    designing decimation filter

    Unfortunately I don't know what CIC decimation filter is. I use polyphase filter for both audio and video. And I am not lucky enough to have Simulink. Anyway, I will give you my 2 cents of experiences. 1. since we will be using a digital FIR filter for decimation, the filter will have to...
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    designing decimation filter

    I am assuming you are in digital data in this case. Here is an app note that may help you understand the topic...
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    About the wavrform viewer on linux

    You can use gwave. Here is the link http://www.telltronics.org/software/gwave/ I had it compile and working a few month ago. There are some minor problem with running it at the beginning. I don't remember what it was. Probably better install from an rpm package. Let me know if you run into...
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    how can I design a buffer

    That depends on your spec and what you want to do. You need to ask youself a few questions 1. What is the bandwidth you need? 2. What is the output going to drive? (resistive load, capacitive load, inductive load) 3. What is the noise level (or the quanlity) of the output? 4. Do you need to...
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    How to install Xilinx ISE 7.1i in 32-bit Fedora Core 3

    This does not seem to be a very hot topic but I don't seem to find a solution out there. So I develop my own. First of all, most of us know we need a few old libraries. libcurl.so.2, libcurl.so.2.0.2, libXm.so.3, libXm.so.3.0.2 We can obtain those from FC2 RPMs. Some people will create a...
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