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Recent content by govandi999

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    Another Challenging Problem in VHDL Design

    challenging vhdl designs Design a Password feeder using behavioral VHDL. In this we have an 8-bit input DATA for the password. We have a signal called ENABLE. If ENABLE ='1' then the input data ie the password is read and loaded in a register. The input DATA is then compared to the data stored...
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    Challenging Problem in VHDL Design : Password Attacker

    vhdl elsif hex In this design, we have to capture the behavior of a password attacking mechanism (Bruteforce) by writing a behavioral VHDL code. Mechanism We have an input "DATA" of size 8-bit. The password would be somewhere between 00 to FF (hex). We will set the input at say 1C (hEX) . The...
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    Reading MATLAB data into a VHDL file

    This is only for writing the data what about reading part?
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    VHDL "after" statement

    why use after statement in vhdl give the full code here
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    VHDL Code for CRC-5 Checksum circuit for USB Error correct

    vhdl code for crc We have to design a module which is a simple CRC-5 check sum circuit that will implement the polynomial (1 + x2 + x5). This polynomial is used for error correction in USB. The block diagram is as follows: We have to design a circuit that takes the 32 bit input and after 32...
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