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Recent content by gonewithstone

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    [Help] FPGA clock multiple cann't work use Xilinx PLL

    In Xilinx Spartan6 FPGA, instantial two PLLs, use output clock as PLL feed back in clock , one for clock multiple(25MHz in, 75MHz Out), another for clock division(125MHz in, 62.5MHz). The test result shows the two PLL can PLL lock, the clock division can generate 62.5MHz clock, but clock...
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    A problem about sdf annotate in post-simulation

    sdf warning There'a a sdf warning in post-simulatio, but I don't know its meaning. Part of the sdf annotate is: "(INTERCONNECT RXADCLK RXAD01 ( 0.110 ) ( 0.110 ) )" The sdf warning occurs in compile is: "SDF Warning: the path from RXADCLK to RXAD01 doesn't have a simple wire connection...
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    A problem for the explanation of +race=all in VCS help

    I know now, Thanks veru much!
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    A problem for the explanation of +race=all in VCS help

    Below is the explanation of "+race=all" in VCS help. But I can't completely understand it. Does it mean if don't use this option, the VCS will ignore the potential race in the source code? And if there's a real race exist in the source code, the VCS won't report it if No use the option...
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    How to disable timing check in post-simulation

    Do you means use the command: *.sim +dump -l runsim.log +vcs+lic+wait +notimingcheck to disable timing check when simulation??
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    A problem in post-simulation

    Thanks for your reply! I have find the reason when I try to fix the SDF warning in compile.log. I' m a newer to do post-simulation, I think it's important to focus on SDF warning infomation in simulation when debug.
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    How to disable timing check in post-simulation

    I use VCS to run post-simulation, but I don't know how to disable timing check in the simulation. Anyone can tell me? Thanks
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    A problem in post-simulation

    I meet a problem when run post-simulation. In the netlist, the cell port RXADCLK is connect to signal \uSub/uIo/uSerdesRx0/RXADCLK, as below shown: HSR \uSub/uIo/uSerdesRx0/HC ( .RXADCLK(\uSub/uIo/uSerdesRx0/RXADCLK ), ................... ) However, according to...
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    [urgent] SDF file annotation problem

    scaled delay is out of range due to the large netlist, the simulation cathe can't dump all the waveform, so you can try to dump part of the waveform, then the problem will be fixed. I have met this same problem. You can refer to VCS manual about $vpdpluson() to dump part of the waveform.
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