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Recent content by Gireesh

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    ASIC companies in PUNE

    asic companies in pune Please list the companies in PUNE working in the area of the ASIC
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    How to calculate the depth of FIFO and what are the designs contraints for it?

    How to calculate the depth of FIFO and what are the designs contraints for desiging it?
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    What are the differences between ASIC and SoC?

    What are the differnce between ASIC and SoC?
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    Assigning multiple high priority interrupt in mcc18

    mcc18 interrupt Hi, How to assign multiple high prioruty interrupts in mcc18 compiler. I am using mcc18 3.02v compiler for PIC 18F6520 microcontroller. Thanks in advance.
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    Multiple High Interrupts in PIC 18F6520

    Hi, I am using MCC18 3.02V as the C-compiler. But i am facing some problem with assigning multiple High priority for different interrupts like TMRO,INT0, RB etc. So please send me suggestion to do this.
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    MBIST controller for Syncronous and asynchronous DRAM

    Hi ramesh, i want to design a Mbist controller which can be used for testing of both the memories.
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    MBIST controller for Syncronous and asynchronous DRAM

    hi, I want to design a MBIST controller for both sync and async DRAM cells. The algorithm that i decided to implement is March C-- algorithm. Please someone help me
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    IEEE1149.1 controller

    standard ieee 1149 Hi, IEEE 1149.1 standars is JTAG standard and u can download the standard fro IEE site. It is a purely digital circuit. The heart of the JTAG controller is the TAP controller. And TAP controller is nothing but a 16 state FSM. So your first task will be to develop JTAG TAP...
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    What is meant by grid error?

    What is meant by grid error? What is its significance
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    Do you need to do post layout simulation for analog IC?

    Re: Post Layout Simulation If post layout simulation has not to be carried out, then where shpuld we consider the efferct of parasitic elements likr parasitic capacitors, resistors etc.
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    Looking for materials to learn BJT layout

    bjt layout Can any one refer the matreials to learn BJT layout techniques?
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    Do you need to do post layout simulation for analog IC?

    Post Layout Simulation hi, I want to know whther it is necessary to do post layout simulation for analog ic,if it has passed LVS checking? Thanks in advance
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