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Recent content by gggould

  1. G

    PLL feedback divider question

    Hi all, Lets say the feedback divider is in div2 mode. 1.If feedback divider input is 1GHz fundmental + 1.01GHz spur, then what does feedback divider output spectrum look like?? 2.If feedback divider generates 1ps jitter, then how does this jitter being transfer to PLL output?? Thanks
  2. G

    Question about PLL Jitter peaking

    Hi, Couple of questions about jitter peaking. My understand is it comes from insufficient PM around Open Loop Transfer Function zero crossing, which is about the PLL loop bandwidth. Am I correct? But typically how do we address the peaking problem? Some paper says lowering wz/bw, other says it...
  3. G

    Question about differential amplifier resistor

    Thanks for the response Dominik and esp1. That is very helpful. So another follow up, how does the original circuit different from this one, from cmrr and psrr point of view? https://obrazki.elektroda.pl/1785936900_1410889835.jpg
  4. G

    Question about differential amplifier resistor

    Hi, Does anyone know how are those 2 resistors in the middle helping performance? And how to choose the proper values? https://obrazki.elektroda.pl/4548811900_1410668669.jpg Thanks.
  5. G

    two/three stage comparator

    Hi, Sometimes I see people add a preamp before comparator. Does anyone know what’s the pros/cons for doing so? I know it is good for reducing kickback noise and metastability. But how about bandwidth? Also can someone recommend any good newer architecture? I only know of strongarm. Thanks.
  6. G

    VCDL requirement in DLL

    Hi, Does anyone know what is the requirement for the VCDL delay time to avoid false locking? My understanding is Tref>Tvcdl_min>0.5*Tref, and Tref<Tvcdl_max<1.5*Tref. I can understand both later parts, but why does Tref>Tvcdl_min and Tref<Tvcdl_max criteria come from? Thanks.
  7. G

    Ldo architecture with good psrr

    Hi, Can anyone recommend onchip LDO architecture with good PSRR performance? I did some literature search but they either need too big output cap to be integrated, or multiple LDOs in cascode which is not practical for low supply operation. Thanks.
  8. G

    Feedback circuit analysis

    Thanks for the comment~~~ But why is the current fedback at input not voltage?? The feedback portion looks like a source follower isn't it?
  9. G

    Feedback circuit analysis

    Can someone give me a hint, like what is Rin and Rout? Here is the pic: h**p://imgur.com/esM1ven
  10. G

    Feedback circuit analysis

    Hi all, I have been confused by how to identify series / shunt / mixing / sampling in real circuit. It is clear to me in testbook two port network example, but hard to figure out when it comes to real circuit. Can someone explains to me a little bit? Also whats Rin/Rout/Av in the following...
  11. G

    why DT DSM ADC has worse SNR then CT DSM ADC??

    Ideally that is the case. But what I heard was due to switching cap nature the DT DSM has more quantization noise folding down to the passband, which degrades DT DSM SNR. Is that the case???
  12. G

    why DT DSM ADC has worse SNR then CT DSM ADC??

    Hi all, Does anyone know why DT DSM ADC generally has worse SNR then CT DSM ADC?? Thanks
  13. G

    why CT DSM ADC more sensitive to clk jitter then DT DSM ADC??

    Thanks a lot!!
  14. G

    why CT DSM ADC more sensitive to clk jitter then DT DSM ADC??

    Thanks for the comment. So basically the extra jitter sensitivity for CT is mainly due to excess T_j*V_dac compared with DT counterpart, but not really quantization noise folding to passband ?
  15. G

    why CT DSM ADC more sensitive to clk jitter then DT DSM ADC??

    Hi all, Does anyone know why CT DSM ADC more sensitive to clk jitter then DT DSM ADC?? My understand is for CT DSM ADC, at outmost feedback DAC output, quantization noise will mix with jitter then fold back to passband. But that should apply to DT version too, right? Thanks gggould
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