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I'm trying to implement a dual processor Microblaze design on my nexys2 fpga. I intend to use the Micron RAM (Micron MT45W8MW16) as a shared memory between both processors.
In order to accomplish that, I need (?) to use a multiport memory controller such as the MPMC IP provided by Xilinx...
I'm using the onboard 50MHz clock. I tried to use a slowed time tick but it's not trivial to incorporate it in the design. Using 0.5 Hz I verified that writing this way does not fill the buffer! But then the reading functionality did not work, I guess I broke something in the design.
Button...
I need some help implementing a design from the book " FPGA prototyping by VHDL examples - Xilinx Spartan 3 Version". It should be kind of necessary for someone to consult the book in order to help me out.
I've implemented the fifo buffer circuit and the respective test circuit documented in...
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