Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thx for the reply, I completely neglected the effect of the current source, but I still do NOT understand why transistor 3 acts as an open switch and just lets all ac disturbance on positive supply pass on the output.
Hello!
After simulate this simple amp (all properly biased), I simulated the graph on the right hand side: Looks like for the low freqs, it's got a PSR of 0dB (ac disturbance in supply, measuring ac at the output).
Isn't that weird? Doesn't 0dBs mean that transistor 3 acts as a resistor? Can...
Hello!
The attached is a loop of a regulator (I drew an extra stage as a square at the output).
There is an extra loop from the Cc capacitor.
I have to admit I have zero theoretical knowledge on how to analyze a circuit with two feedback loops.
Let's also assume that I cannot change the...
Thank you that's a very helpful generic approach.
I am obliged (work restrictions) to hide the "rest" of the circuit, but this is not a standalone amplifier, but part of a feedback loop.....That's why I mentioned that I'd like as few changes as possible-you're totally right that CMFB would...
How to change VDS/VDSSAT
Hello!
I have a funny very basic but very confusing situation.
I have the circuit you see in the graph: a tail transistor M1 has a set gate voltage C, so it's acting as a current source.
The branch I care about has a current source (transistor M3, with gate voltage...
Unbelievable that I have to make such comments in a scientific blog, but @Ratch, I hope you're not a professor, cause your students must be suffering from your way of thinking and expressing "your truth" (possibly scientifically correct) over the "common language" used everywhere: I will not...
I have a question: I scanned a series of timeshots, and i will go through them, the way i like to think about capacitors (maybe that's where the problem begins)
1: If i connect a totally uncharged capacitor on one side to Vdd, then immediately the other side will show Vdd (for a fsec only). So...
Hello!
I want to model a cadence block (analog) and interact with the nearby analog blocks, but with a VHDL model (using VHDL AMS for that reason). The cadence block (cell) has many inputs (pins) but i will only model it as a buffer, output=input. So, i have this code:
Library (......)
ENTITY...
Re: Verilog Question about instantiating
Thx for the reply, i re-read the code this morning, but my question remains: How can i tie the output of the "other module" to any value of this module?? Shouldn't i only tie the inputs of the other module, and USE the output the other module produces...
First of all i want you to forgive me for placing this Q here, where should I? didn't find any match for verilog/vhdl questions!
And now the question, which is pretty basic: when i instantiate a module in another module, and i open a parenthesis to give values to the inputs/outputs, i have...
From the Gray Hurst Lewis booK? My mistake it's the w3dB. I have a translated version, so if they follow the same ordering, chapter 7(frequency response) for the common emitter configuration, the pole 1. But this gives me no answer as to where the wunity formula comes from
Hello!
I am a bit confused about the unity frequency of a MOS transistor.
I see in one book that wunity=gm/Cgd, which makes sense when the transistor is ideally driven (by an ideal V source)
I see in Gray/Hurst book that wunity=1/[Rsource*(Cgs+Gain*Cgd) which makes sense if there is non ideal...
Guess: Suppose a one pole simple oscillator (which only builds relaxation oscillators, but still) : An oscillator transfers time information to amplitude information when excited.... So we have an amplitude changing, but in order to make it "periodical" then the slope is not enough. The system...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
