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Jeevan , can you discuss why exactly you need hold anaylsis before CTS...Hold fixing is not in true sense an optimization process, its a degradation or relaxation step...
since we have realistic clock skew, latency, and delay values POST CTS, thats why we do hold fixing after analyzing the...
Before CTS, or lets say at the FE level, we just have wire load model to take care of the parastitics and clock is ideal, this situation is optimistic when we compare w.r.t POST CTS situation.
Lets accept that hold and setup are complimentary stuff, each one of them eats up in other's margin...
OCV is modelled by derating factor, uncertanity is independent of OCV. Correct me if iam wrong.
Latency is modelled by set_clock_latency, not by uncertanity.
I think you are correct..
Before CTS we just have ideal clock network..i.e. no skews, no clock latency(network or propagated), thus we provide an uncertanity value to model(clock skew + jitter)..POST CTS we have a realistic clock network wid realistic delays, and skew information. Thus the...
Level_shifters are not getting inserted in my design, there were no errors while reading the UPF, and the tool identifies the need of level shifters but cannot insert them.. I ran analyse_mv_design - level_shifters and got these messages:
Pin: add/U6/Z;
Type...
one remark: Using different scopes we can use same name nets across different power domains...
For ex: VDD_m at top scope can be accessed by VDD_m while at block level by BLOCK/VDD_m.
---------- Post added at 07:57 ---------- Previous post was at 07:54 ----------
A query about power switches...
hi folks,
Iam trying my hand at power aware synthesis using synopsys upf flow. Here i will try to raise some doubts and share my experiences about this flow.
Lets start with the most basic stuff create_power_domain command...iam unclear about importance of different scopes...can't we just...
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