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Recent content by gavin168

  1. G

    DLL question - duty cycle of input clock is 30%~70%

    Re: DLL question can anyone give some suggestion for the duty cycle correct? And, Is it better to use PD or PFD? Thank you.
  2. G

    DLL question - duty cycle of input clock is 30%~70%

    Re: DLL question thank you coolstuff07, but 40MHz~240MHz clock with 30%~70% duty cycle, to get 50% duty cycle for whole range. Is it difficult to make a duty cycle corrector?
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    DLL question - duty cycle of input clock is 30%~70%

    DLL question I am designing a DLL project, working range is 40MHz~240MHz, but the duty cycle of input clock is 30%~70%. I plan to do: 1), in order to lock correctly, the delay will be forced to below 1 period when initial. so i plan to reset the vcntrl to be VDD? 2), for the the working...
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    how can i improve my PLL?

    Hi, guys, the Attachment is the PLL loop simulation result. my VCO control voltage look not very stable. how can i improve it? ( my reference clock is 8 MHz. and VCO is working at 200 MHz. the Kvco is about 520 MHz/v, Charepump current is about 4 uA and main cap of LPF is about 150 p) And the...
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    questions about Delta-Sigma Fractional-N PLL

    pll site:www.edaboard.com Hi, guys, I am studying the Delta-Sigma Fractional-N PLL. there are somethings I don't understand. First, what's the difference between the classical Fractional-N PLL and Delta-Sigma Fractional-N PLL? Is it like this case: For classical Fractional-N PLL, the...
  6. G

    how to calculate the natural frequency for PLL?

    calculate natural frequency Hi, guys, If we already have the parameters for passive third-order LPF, how to calculate the natural frequency and damping factor? we can find the equations to get these for second-order LPF. but I do not know how to get those for third-order passive LPF. thanks.
  7. G

    how to generate 4phase clock

    Hi, guys, How to generate 4phase clock. don't use PLL, DLL. And how to generate a clock whose frequency is twice of input clock and duty cycle ia also 50%? Thank you.
  8. G

    question about phase interpolator

    basic phase interpolation sorry, rfsysterm, what is pure CW's? thank you
  9. G

    question about phase interpolator

    phase interpolation Hi, guys, hi, Mohamed, how are you ? Now I am doing an analog phase interpolator. do you know something about this. I have some trouble about this. First, the clock(coming from VCO) to be interpolated can be rail to rail or not? second, I use traditional archiecture...
  10. G

    How to generate a reference current of 5uA?

    Reference current Is there any good idea to make current reference with indenpendence of Temp and Process. all component should be on-chip. It is better to not use resistor, because it is too hard to make a precise resistor in silicon.
  11. G

    How to simulate Bandwidth and Phase Margin of a PLL

    After open the PLL_2 in the work_116 khouly upload, then how to do the PM simulation? It is said LTI viewer should be used? but i do not know how to complete it? Thank you
  12. G

    how to setup a simulink model for PLL

    phase locked loop simulink To RFDave Do you mean we should figure out the LPF accordingly to the formular at the Dean Banerjee's book? Because I am interested at that how simulink to do the PM simulation. I want to pick it up.
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    how to setup a simulink model for PLL

    simulink pll model Hi, RFdave, I want to do behavior simulation of PLL. It is said simulink model can do PM simulation, But i don't know how to do it.
  14. G

    how to setup a simulink model for PLL

    pll simulink Dear all, I want to do behavior simulation for PLL. I got a model at simulink demos as the attchment. would you have a look? how to do the PM simulation by this model? If it can not do it, what kind of simulink model for PLL can do the PM simulation? would you help me? thank you...
  15. G

    about the disign process of pll

    I will begin to do as khouly had said. thank you
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