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Hi,
Our team wants to design LED driver chip. But we do not know the confirmed flow in Cadence or other tools.
For the LED driver circuit include some Discrete Element such as Transformer, optocoupler...
These elements do not have good spice models for simulation(some have pspice model, but how...
Hi,
Would anyone can tell me how to export hspice netlist in IC6141, please?
In this cadence version, the hspiceS simulator has been removed...
I just only get the netlist by export the CDL feature...but, the cell of analogLib can not be export together...
Thank you.
Best regards!
Hi, everyone.
How to set the Array value in Verilog-A, please?
For example, I defined as follow:
output [7:0] dout;
voltage [7:0] dout;
I want to use the initial_step function to set the dout[7:0] to some value (every bit with a different value), how can I do that?
As the generate function...
Hi,
I have some difficulties in generating SPEF file from Calibre xRC.
I set the rule file as following:
PEX NETLIST DISTRIBUTED "soc.pex.spef" SPEF PRIMETIME SOURCE
And the following are the csh env:
setenv PEX_FMT_SPEF_NAME_FILTER_MODE "X"
setenv PEX_FMT_SPF_LUMPED_MODEL_MODE NONE...
Read the MW output from ICC to Astro, and use to above command to add_text automatically, then output stream from Astro.
I have successed.
Hope this method can help others!
Best regards!
Hi,
Could anyone tell me how to add IO port Text in IC Compiler automatically, please?
Without these IO port Text, LVS/xRC in Calibre will fail.
As I know, in Astro, the following commands can do this:
dbAllowToAddPGIOText #t
dbAddIOText (geGetEditCell) "*" "*" 41 20
As my design has 218 port...
Re: DC -topo Error
Thank johanlo.
I have found the reason. There are something wrong in the DEF file from Encounter, I changed a DEF file from ICC, the DC -topo worked well.
Hi, everyone.
I want to input the floorplan information of Encounter to DC(topographical_mode) to improve the timing of the design. The floorplan information is DEF file format, and it can be read into dc -topo by extract_physical_constraints command correctly, and the "compile_ultra -scan...
Hi, LVM
I am sorry I did not describe the meaning distinctly.
My question is why there is a zero in the AC result at the frequency near the main pole which makes the phase-margin bad.
Because this zero is near the main pole, so I think it is caused at the output node, but I do not know why.
This...
Hi, I am designing a full differential OTA which is a Folded Cascode amp.
There is something strange in the AC result.
Can anyone help me analyze it？
Thank you！
The AC result is the OUTP node.
Hi, mengcy
I added the Rlaod=400 and the Cload=500pF when simulation.
The ClassAB output stage is the Push-Pull, Common Source Amplifier.
The output node of the main amplifier is good.
But I can not find the reason.
Thank you!
Best regards!
Below is the step response of this ampilier with...
Hi,
I am designing an amplifier for a DAC output driving application. And the structure I chose is Rail-to-Rail input stage + class AB output stage, and the main ampilfier is folding ampifier with gain boosting assistant amplifier. The output driving ability requied is 400Ω+500pF, but the AC...
modelsim tsmc18.v
Hi,
I have tried many method to fixed the "XXX", delay th clock, change the reset signal, but the "XXX" is still there. And when I change the clock frequency, the origin of "XXX" will change. and when lower the frequency, the "XXX" will comes late. Frequency = 100M, the...
modelsim clock delay for hold
Thank you, WzWzWz.
You mean I should change the testbench to fix the XXX in the compiled simulation or post-simulation, is that right?
I thought I should add the same testbench to the RTL and compiled simulations and got the same results before, so as the ensure...
how to set clock frequency at 100mhz in modelsim
Hi, shanmugaveld
I did not add the std cell delay to the simulation. I just added the compiled netlist, the technique library verilog file and the testbench to modelsim.
When I do such simulation, should I add the sdf (generated from DC) to...
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