Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
for each iteration the delay is fixed.
in each loop i am driving each bit of the wr_data.
initially the data was driven at posedge of clk, but now i am using this
@(posedge clk_sdcard_slot_in);
for (int i=data_width-1; i>=0;i--) begin
data_dev_slot[i] <= #del wr_data[index]...
sorry for that
my timescale is 1ns/100ps
the delay that i am using is
int del = urandom_range(0, 9);
thereafter i am using
data_dev_slot[i] <= #del wr_data[index];
i am running this in loop so that i get a different delay everytime. but i am getting a delay of 1200ps, 200ps, 2400ps...
Hello,
I am new to system verilog. I am trying add a randomized delay to a module.
i tried doing this, but didnt work
del = $urandom_range(0, 9);
data_dev_slot[i] <= ##del wr_data[index];
can somebody please help me on this.
Thanks,
Rohit
Hi Raul,
Thanks for the reply. when i plotted the response of the filter that you gave. It looks like a multinotch filter.
I ve attached it. Please have a look.
Hello RaulPinheiro,
Thanks for the reply.
Am I doing anything wrong here - b = [-0.2 0 0 0 1] and a= [1 0 0 0 -0.2]. or is my difference equation correct?
Thanks for you help
when i plot the frequency response using matlab with filter coefficients b = [-0.2 0 0 0 1] and a= [1 0 0 0 -0.2] i got a flat spectrum (here N = 3, g = 0.2). or for that matter with any value of N, i got a flat spectrum.
i used freqz(b,a).
---------- Post added at 09:47 ---------- Previous...
Hello,
I am designing an all pass filter which is a part of a reverberation generator for audio inputs. I am implementing it in verilog.
The difference equation that i am using is
y(n) = x(n-N) - g*x(n) + g*y(n-N);
g - gain, N - filter order
the transfer function is H(z) = [-g + Z^(-N)]/[1...
one more question yoramgr
can i use display in a test bench?
can i pass a 2 - D array from a test bench to verilog code.
i am trying to send an array of data 8 bit wide and with depth 110592
its like [7:0] im_b_x[110591:0]
Thanks a ton yoramgr!!! :razz:
I have used readmemb. I am able to read from a file and write to a file in verilog properly. I have some issues to solve in MATLAB now.
thanks a lot.
I didnt have to use for loop for readmemb. it reads the whole file at a time
for $display i needed to use the loop...
i have made 3 different files for R, G and B files. now i am just trying to read R the file.
i hve attached the text file. please check it.
what might be the error in this code
module Edge_Detection();
reg clk;
integer fd;
integer i;
integer r;
wire [7:0] im_r[110591:0];
initial
begin
fd...
man this is getting frustrating...as u had suggested i tried generating 3 different files for R, G and B.
when i open the text file to check the values the file for G is getting generated properly but for R and B the txt files are showing garbage values.
so i am going to try with only one...
Hello FvM,
thank you for you reply.
I have not yet used any one of them...but using which of these, readmemh or fread will i be able to read the complete 2D array and store it as a 2D array.
so that i can process the data by indexing the row and column.
hi yoramgr,
this time i have to read a 2-D array...
actually I am processing an image this time. the image is of 288 x 384 x 3 array.
i have taken the pixel values into a txt file in hex format from MATLAB. and as you told me last time, the values in file are hex values and the file itself is...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.