Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by G.Satheesh Kumar

  1. G

    Difference bettewen floorplanning and placement

    hai.. floorplanning is starts with creating physical only pad cells and defining their location and placing them. defining size and shape (by aspect ratio) of our block. defining PG pad rings for power continuity. specifying ignored routing layers , placing the macros by following some macro...
  2. G

    what is the process in pvt?

    thanQ dick_freebird for ur response .. so 'process' is nothing but the combination of effects of Vt,tox, mobility and delta-L... right ?? i've an idea about Vts,tox & mpbility but i don't know about delta-L.. can u plz xplain about that??? and how these factors are considered for process ???
  3. G

    what is the process in pvt?

    hi all. . . Can any one tell me what is the process in pvt conditions ThanQ
  4. G

    height of the standard cell in 40 nm and 90 nm technologies

    hai all.... can anyone tell me the height of the standard cell in 40 nm and 90 nm technologies ??? thanQ
  5. G

    setup check and hold check on clock gating paths

    hello every one... can anybody clearly explain about checking of setup and hold violations in clock gating path
  6. G

    calculating cell delays by using non linear delay models...

    tanQ @artmalik.... but can u explain in some more detailed manner..!!!
  7. G

    calculating cell delays by using non linear delay models...

    hello everyone... can anybody explain the process of calculating the cell delays by using non-linear delay models and composite current source techniques.... thanQ...!!!
  8. G

    reason behind hold fixing...

    hello everyone... can anybody tell me that the reason behind the fixing of hold time only after routing process thanQ
  9. G

    what if a flipflop getting set and reset at a time ?

    we have to take dat condition as a metastability state and we simply ignors it ....generally it is happens only in SR type when the inputs are 11
  10. G

    what do you mean by glue logic???

    thanQ for ur reply but can you please explain it in some more detailed manner...
  11. G

    what do you mean by glue logic???

    hi, can any body explain what is glue logic , where and how this logic is used in physical design thanQ...
  12. G

    what do you mean by electro migration???

    hai everyone, can anybody explain about electron migrtion in physical design....and where it used in physical design thank you...

Part and Inventory Search

Back
Top