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flash adc used little than pipeline and sar
but flash adc can work very fast, giga-hz sample rate
read-channel chip need 6bit giga-hz flash adc.
you can learn flash adc firstly and design a pipeline or sar adc. it's helpful
"PD" only hold the phase error between reference and feedback signal constant (zero or not), if "PD" is a analog multipler, the phase error maybe not "0". and the frequency of reference and feedback maybe not equate
so, your figure is right! because the phase error is constant on "PD".
post layout simulation hspice
you can't run hspice directly with spectre.
you should change hspice netlist to spectre netlist firstly
you can directly extract RC netlist from layout on spectre mode with proper tool.
mim capacitor layout
MIM capacitor have "CTM dummy" layer
you could connet mim capacitor bottom plate with M1~M4, but outside "CTM dummy".
for example, if your CTM CAP is "M4-CTM-M5", then you couldn't put "VIA34" just under capacitor. But you can draw a Metal4 line from CAP bottom plate to...
I can't using integrated inductor. Because the working frequency is very low, so CMOS tech inductor very large, and Q will lower. bonding wire inductor is small.
I think shunt feed amplifier maybe well. But how can I improve NF?
IEEE JSSC 2004.02 have a paper about thermal noise canceling, But I...
I want to design a LNA work on 75MHz~108MHz (FM Receiver frequency band)
But I find it difficult to do.
My specifiction is :
CMOS tech (0.18um), NF<2dB, integrated on receiver. without external inductor (exclude impedance matching inductor)
Can someone gime me some advise or thesis? thanks very...
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