Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
interdigital capacitors
hi
in general in hfss for design capacitances we have problem, but usually we can simulate capacitace with one boundary condition plane.
you must first in where you want to have capacitance draw a squre plane, then select this plane and assigne LUMPED RLC Boundary to...
hi
I think 2.5 dB is unusual.
the main loss in combline filter is reffered to lump capacitances and dielectric loss have a little effect in this filter.
but I must know that what is your substrate and I think you use ideal capacitances, so if your loss tangent is less than .003 (such as...
Re: having problem with C++
PLease send me error message during compiling
and if you can, send me your source code maybe there is any problem in it.
Trust me :D
best regards
fredy
Re: HELP!
hi
first how do you validate your design? (which simulator)
second what is your load and your transistor that use in your design?
and at the end My ANSWER IS
You must another filter instead of T-match section
with your answer maybe I could better help
best regard
fredy
COMBLINE FILTER
I want to design combline filter in microstrip form and in L band(2-4GHz).
I want to see the shematic of some practical design (please send me if
any pictures are available) and I want to know how the capacitors of
this type of filter (in microstrip form and in L band (2...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
