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Recent content by fredflinstone

  1. fredflinstone

    automotive analog IC design inverview

    also learning about EMI/EMC effects in design would help.
  2. fredflinstone

    Should I pick up npoly or ppoly as a resistor loads?

    npoly vs ppoly resistor i think you can use either of the two in your design.
  3. fredflinstone

    Puzzle SAR ADC simulation ???

    hello wls, It sure will help you if u do block level parasitic simulation. At 125 degC normally the devices gets slower... the critical path in your SAR logic is something to look at. Also the comparator may not be able to amplify the input to sufficient levels before giving to latch.
  4. fredflinstone

    Puzzle SAR ADC simulation ???

    which part of the circuit is failing? is it a functionality error or performance degradation?
  5. fredflinstone

    relationship between gm and Ids

    your transistor needs to be in saturation. Ids in (1) (2) and (3) is the drain source current when the device is in saturation.
  6. fredflinstone

    Inductorless dc dc converter

    Hi all, I am planning to design a inductorless dc dc converter (switched cap dc dc converter). Please.. can anyone give me some good books/papers on this as I am new to dc dc converters. thanks in advance, fred.
  7. fredflinstone

    some question about sar adc

    The preamp will help in reducing the latch offset. But the preamp itself will have offset and hence that has to be cancelled. And you need not calibrate the capacitor DAC to get 10 bits .. There is a good paper on Comparator Offset cancellation by C.Enz. It will help you in designing...
  8. fredflinstone

    What's the difference of the SC-70 and SOT-23

    sot sc70 footprint the following link may help.. **broken link removed**
  9. fredflinstone

    What's the difference of the SC-70 and SOT-23

    sc 70 and sot difference SC70 has smaller footprint than SOT23 ...
  10. fredflinstone

    Guard rings around pmos

    Then I think you can use one sinle n well guard ring around the whole block. Coz u only need to worry about the substrate noise coupling from blocks external to the current mirror block. Individual pmos to pmos isolation may not be required. btw, why do u want to short the source and backgate...
  11. fredflinstone

    Guard rings around pmos

    do these set of PMOSs form a current mirror? then its better to place them near to each other for better matching. Since you told that they only have gate terminal common and S and D are not shared you have to place them in different n wells. If the switching activity of the circuit is critical...
  12. fredflinstone

    Guard rings around pmos

    substrate contacts reduces ur substrate resistance and hence whatever noise injected by the device to subs will have low resistance path to ground. If you have an nwell guard ring then it will isolate the device from noise from external sources reaching the device by providing isolation. So...
  13. fredflinstone

    layout dummy transistors

    yes u can use ... as far as i know there is no issues on having dummy transistors for PMOS/NMOS irrespective of their backgate connection.
  14. fredflinstone

    heavy or lightly doped?

    lightly doped would give higher resistance not lower
  15. fredflinstone

    Why noise response have some peaking at high frequency in amplifiers?

    noise The noise peaking at high frequency may be because of chopping at the input of the opamp. This modulates the low freq flicker noise to higher frequencies outside the signal bandwidth which can be filtered out as Old Nick pointed out.

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