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hello wls,
It sure will help you if u do block level parasitic simulation. At 125 degC normally the devices gets slower... the critical path in your SAR logic is something to look at. Also the comparator may not be able to amplify the input to sufficient levels before giving to latch.
Hi all,
I am planning to design a inductorless dc dc converter (switched cap dc dc converter). Please.. can anyone give me some good books/papers on this as I am new to dc dc converters.
thanks in advance,
fred.
The preamp will help in reducing the latch offset. But the preamp itself will have offset and hence that has to be cancelled. And you need not calibrate the capacitor DAC to get 10 bits ..
There is a good paper on Comparator Offset cancellation by C.Enz.
It will help you in designing...
Then I think you can use one sinle n well guard ring around the whole block. Coz u only need to worry about the substrate noise coupling from blocks external to the current mirror block. Individual pmos to pmos isolation may not be required.
btw, why do u want to short the source and backgate...
do these set of PMOSs form a current mirror? then its better to place them near to each other for better matching. Since you told that they only have gate terminal common and S and D are not shared you have to place them in different n wells. If the switching activity of the circuit is critical...
substrate contacts reduces ur substrate resistance and hence whatever noise injected by the device to subs will have low resistance path to ground.
If you have an nwell guard ring then it will isolate the device from noise from external sources reaching the device by providing isolation.
So...
noise
The noise peaking at high frequency may be because of chopping at the input of the opamp. This modulates the low freq flicker noise to higher frequencies outside the signal bandwidth which can be filtered out as Old Nick pointed out.
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