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Hi, for those with experince, can you please help me understand the reason for device output resistance (ro) change from scheamtic to post-layout? It's for a 7nm technology. I checked the current and it's almost the same. For the reference, Ids only -1%, gm is also almost the same. But I...
I see that can help, thank you. Maintaining high UGB while doing this across process is a little bit challenging. But exploiting it not aggressively can help a little.
As mentioned, this amplifier is used in a CMFB circuit which I haven't shown. Regarding the stability problem of this amplifier, just like other stability simulations, a unity feedback is applied (for the worstcase). So consider input (Vin) directly connected to output (Vo).
Hi, I want to use differential to single-ended amplifier architecture for the error amplifier in my CMFB loop. I see that in my design, the amplifier does not have a good phase margin. But I haven't seen much information in textbooks about how to compensate for such an amplifier. Razavi warns in...
Hi, I have a simple sample and hold circuit. The resistor is 100 ohm, the switch is ideal (Ron=1u, Roff=1T), capacitor is 500fF. If there was no switch and I run a simple noise simulation in virtuoso, for PSD, I see exactly 4KTR in low frequencies with a LPF shape (due to the capacitor), and if...
Sir, input is just biased to the common mode. But I haven't applied any input signal. Whether I apply input or not, I see the same behavior. I don't apply input because I wanted to make sure the ripples are not from signal coupled there.
Thank you for your response. I don't apply any input in this simulation. Can you please elaborate what exactly you mean by input overdrive and how it can cause ripple in supply inrush current?
Regarding schematic, unfortunately, I'm not allowed to share. It's just a non inverting amplifier with...
This is simulation. At this point, there is no extracted view and I don't have any actual or parasitic inductance available in the schematic. Although, I understand sometimes impedances can become inductive even when there is no inductance. The feedback network consists of capacitor and resistor...
Hi,
I have a opamp based PGA. When I look at the inrush current (enabling PGA, and looking at the supply current), I see ripples in the current and I can't justify it. During startup, the capacitors of the nodes are acting as short so I expect the peaking, but then I expect an exponential decay...
Hi,
I have a basic question. If I want to implement a filter (first order) using opamp, I wrap a parallel RC around the opamp as shown below. Let's say I want to have a gain of 0dB (RF=RI). If I have a healthy phase margin, does it matter if my UGB is very close to my BW of interest for my...
Hi,
Does anybody know fundamentally how ADS does optimization? I’m amazed that it can do it so fast and it doesn’t seem intuitive to me. I was wondering about the measure it takes making this possible.
And why Cadence doesn’t have this option?
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