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Recent content by fpga_quest

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    importing user peripheral to edk

    hai.. I have one spi ipcore done in vhdl,I wish to interface this ipcore to microblaze processor .suggestions are always welcome..please comment
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    methods for dividing the clock in fpga

    thanks for ur comment....!!!,I cannot be done iN FPGA..best method i think is counter or dcm..!!!thank u all for all ur valuable comments
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    methods for dividing the clock in fpga

    thankx for the comments...problem I am facing is..when u divide a frequency there will be a fractional part,so how to compensate that fractional part in counter division..!!!i dont know how to implement the fractional counter...can i get any sort of good reference..!!!
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    methods for dividing the clock in fpga

    I am new to fpga based hardware designing, I having one requirement,i have one 200 Mhz clock,I generate different frequencies close to 200Mhz.i wish to do the same with clock division,but if feel it is not possible to generate,is there any other way to generate these frequencies without the...
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    FPGA timing vialation

    Dear all... I am new in RTL designing ..I am facing one problem in my design.my design is having an input clock of 100MHz and generate some of the frequencies in my design like 160,50Mhz ans some more...so wat my problem is..i have one signal(Register) which is clocked by 160 MHz and i am...
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