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clock division
there are at least two reasons why gates should be prevented along the clock tree from front end netlist:
1. too many gates on the clock line will typically screw up the duty cycle
2. gates will complicate CTS procedures.
It is allowed to add muxes and xor or inverters prior to...
I am asked to take some spice analog netlist and use synopsys tools to convert them into digital stimulus. Feeding these stimulus into the digital interface to check the functionality. I think it's nanosim tool. Does any one know how to use it along with cadence ncsim and the flow about it? I...
I only used ports as ScanClock. But for scan shift/scan output stuff, I used internal signals, because I did not manually connect them to ports. I left the job to stitching tool to connect them.
set_dft_signal -view spec -type ScanDataOut -port ioxxx -hookup_pin "uxxx/xxx"
So it seems that...
hi pra, i agree with your point. but i think that kind of expression can only apply for verilog.
wut should be used for vhdl? i know in ncsim you can use some special function, but it can only be recognized with ncverilog.
Spare cells
as far as i know, there are two ways to put spare cells. As a front end guy, i always put some NAND/NOR/INV/OAI/AOI/AND/OR spare gates in my design. Also 2 scanable FF for each clock domain. After the netlist down, backend will put bunch of spare gates everywhere uniformly in the...
rtl gate level
I don't know if there are any tools you can use to transfer the synthesized netlist directly to a generic verilog independent to the technology.
but i guess there are two ways to make it true:
1. other than the netlist, define a mapping file to map the gates instantiated in the...
slow corner temperature
:| fast nmos/pmos?
u sure?
i will just specify a single FAST/SLOW to indicate that...
is there any parts marked as "fast slow corner parts" or "slow fast corner parts"?
fast fast corner
does any one know the meaning of fast fast corner and slow slow corner?
why there are two fast and two slow? what does they mean respectively? wafer fast? process fast? :|
thanks
Quick question. How do you guys handle async reset in your design.
Should I use the OPT1 coding below, or should I use the OPT2 coding below. If I use OPT1, then even if the iclk2 is not present, the flops with orst2 will still be reseted. If I use OPT2, then orst2 should have no recovery time...
The normal DDS have a low frequency resolution. I.e. if the reference clock is 200MHZ, the frequency resolution is normally also 200MHZ.
This is not very nice, since you cannot have a clock of frequency 160MHZ, only 200MHZ, 100MHZ, 66MHZ (5ns, 10ns, 15ns etc) available.
To achive smaller...
vlsi university + us
Silicon valley marched into a cold winter since the mid 2008. Now many big companies laying off people, not only semiconductor business, but technology in general. Most consumer electronic ic companies are not doing well. But network/ethernet and rf chip companies seem to...
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