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Dear all
It might be an easy question, but I have had hard time to figure
I need to increase the font size of components' values. I use NCSU's "create publication schematic" option to generate schematics and parameters' names and values for publication purposes. Then, I use a plotter to export...
Dear erikl
Thank you for your recommendations all the time. It really helped me figure out.
The problem is still in the air, but I'm very close to the conclusion. As you see my customized layouts, I always use multiplier for big MOSFET's. When I got rid of all multipliers, especially the...
Dear erikl
The two pMOS's (p43 and p48) which are the starting up circuit turn off completely. The id from both pre&post layout are zero or very close to zero
The voltage at "net 131" = "CP_in". For example, when CP_in is supplied with 10V. The net 131 gets 10V from both pre&post layout
Thank you
The pdf file shows the output comparison. This is what has happening
Even though I increased all the paths at least three times, it gives me the same results
I'm pulling my hairs
Dear erikl
When I connect the right side of the input opamp to the output, I couldn't get enough regulated voltage as 2.5.
The node voltage at the top reference (which goes to the opmap) is 1.675/1.856, where schematic/extracted respectively.
The node voltage at the bottom reference (which...
Re: Result difference from schematic and layout simulation for a regulator
Dear erikl
When I changed the CP_in there is a difference again between the schematic and extracted. Changing the channel length on the pMOS's did not help due the the deep saturation
I moved the bulk tabs also closest...
Re: Result difference from schematic and layout simulation for a regulator
Dear erikl
Based on your theory, I inspected on the PMOS's at the output. The minimum channel length for any MOSFET in this regulator is 1.95um. However, I used 0.6um for the four PMOS's at the output. As soon as I...
Result difference from schematic and layout simulation for a regulator
Dear all
I have spent enough painful hours and days to figure what has gone wrong in my design.
I attach all files (schematic, layout, and extracted). No problems and no errors with DRC and LVS.
The CP_in is the input...
PLL is always good
ALU, DAC, ADC, etc. The difficulty level comes not from designs, but the specifications on the devices. Putting them in low specifications such as low bits, low resolutions will make it easier.
Dear all
I am looking for a commercially available "Native Transistor"
I am building a charge pump that converts RF power to DC, typically composed of diodes and capacitors. Every diode has its own forward voltage drop which is a loss of power. That's why designers use Schottky diodes.
The...
Dear All
I am designing a stimulator that can inject a steady 5mA. To be independent on the load impedance, a current mode stimulator has been chosen for my design. I have researched and designed five different circuits, and the attached one is the best in results so far.
In my application...
Dear LvW
Thank you for your comments.
"Frequency of oscillation" is more accurate to say. One thing that I disagreed with you is "only sinusoidal waves have a "frequency." Any kind of periodic waves is supposed to have frequency (sinusoidal, square, triangle, saw, etc). As long as there is a...
Ok. Thank you for all answers
Of course, I read the Wiki because if you google "relaxation oscillator", the top link is from the Wiki. Nobody can miss it. However, it's not for my case
The C1 is a capacitive sense (it varies). That means the oscillator keeps oscillating in different frequency...
I have a hard time to find a time constant on a relaxation oscillator I have (attached). This is a comparator-based oscillator
I have calculated the transfer function on it. I tried to obtain the time constant from the transfer function, but not easy.
Can anyone help me?
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