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Re: Difference between n well drawing and n well pin layers in cadence virtuoso layou
Hi hetira,
If in your schematic the PMOS Source(S) of the inverter is connected to VDD then it should be fine.
Normally NWell is tied to positive potential which is VDD then it is not short circuit it is...
Hi Junus2012,
There is a company called SILANNA www.silanna.com in Australia and they are semiconductor with FAB and using SOS process.
You might want to check it out.
fixrouter
resistance of path
you can do the EM/IR drop but not resistance using the tool VAVO(Cadence). But this will cost you too much in terms of $$$.
the cheapest way of computing the resistance of specific path is to do it manually.
cheers
path off grid
hi henrywent,
offgrid is normal in vxl when you do a 45 degree path...the only way to fix this is to make a polygon on a 45 degree line.
hope this helps.
cheers!
Hi AdvaRes
The capacitor and the resistor bulk connection should under the local NWELL if it is connected to Supply (vc.
As far as i understand in your schematic that the capacitor and the resistor bulk connection is connected to supply(vc).
fill me in some information to help you more.
cheers
Hi AdvaRes - sorry haven't check my inbox lately.
First thing I want to ask you.. do you already have the PADS or I/O(Input/Output pads) layout for you to continue and make the PAD rings etc.
PADS also has some small circuit protection in which one of the connection is to the core of the...
hi cdz - you're right that the current depends on the Width of the wire...if it's high current then you need wider signal wire you can compute the current handling of different metals.
The distance of the metal from point A to point B of the signal concern. e.g. you have 1micron width of metal...
Hi santom,
ntap contact -consist of the following layers (NWELL/NPLUS/ACTIVE(OD)/METAL1/CONTACT) - to be connected to VDD or power supply or you can surround an ntap ring to your PMOS type elements.
ptap contact -consist of the following layers (PPLUS/ACTIVE(OD)/METAL1/CONTACT) - to be...
lvs short
what verification tool are you using?
if you're using calibre tool for your verification you cannot parse or continue your lvs run unless you change your Calibre >Setup> LVS Option then untick Abort LVS on power/ground net errors.
if that's not the case and you have an LVS result...
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