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verilog-a
I use the kundert's VCO modeling and find some problen when do simulation in Hspice.
The problems: the VCO works well under 10uS, but the output is wrong when tran simulation larger than 10uS.
I don't know what's wrong?
you can get the result use attachment hspice netlist...
Tline_sim.scs netlist file
Tline.va the veriloga model of transmission line
There are two models in tline, pls see line 8 and 9, you can choose anyone and disable the other using “//”.
There are problems when simulating
1. use line 8 model
error:grammar: syntax error, at line 8 in...
thank you for your method.
I want know the cable loss along freq from low to high, the manufacturer just provied the loss at one spicyfied freq. So I have to measure it.
I want to model the transmission line with resistor, cap and inductor, so
I can simulate the E1 /T1 transeiver system, the bit rate is 2.048M/1.544Mbps.
Do you have any simple models about the coaxial cable and Twisted pair line, relative papers and books are also good.
thanks.
coaxial cable transmission line
I want to model the transmission line with resistor, cap and inductor, so
I can simulate the E1 /T1 transeiver system, the bit rate is 2.048M/1.544Mbps.
Do you have any simple models about the coaxial cable and Twisted pair line, relative papers and books are...
As I simulate the OPA circuit, I am always confused about the test bench.
Can you provide some opa test benchs for me? website, paper, book are
all ok.
thanks
According to Sze's book, the vth0 will decrease as gate length become small with constant width.
But I conclude from TSMC 0.18um technology that Vth0 increase with length reducing.
I found that ,W=10um L=10u, 4u, 1u, 0.18u , we got the corresponding Vth0=0.43mv, 0.44mv, 0.48mv...
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