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Recent content by filip.amator

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    Level shifter 1.8V<->3.3V

    Hi All! I am looking for an inspirartion for a level shifter circuit (unidir.) between 1.8V and 3.3V digital systems. Sadly, I can't use dedicated chips - they must be radhard and SEL free and I couldn't find proper products on the market. The only option is to use discrete components. Max...
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    [SOLVED] Device Support for MAX10 FPGA

    The device with Vcore listed as "1.2V,1.5V" means that you can use this device with Vcore=1.2 or Vcore=1.5V. It does not mean that you have to provide two different voltages.
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    UART Problem on CPLD c-m240 board

    Before doing any work on the evaluation board you can check if your design works by doing simulation.
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    14 bit adc output to 5 bit data conversion in VHDL

    Try using resize from numeric_std on signed data type. https://www.csee.umbc.edu/portal/help/VHDL/numeric_std.vhdl
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    channels in GNSS receiver

    Yes, according to the diagram this receiver can only process/track three channels.
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    VGA to HDMI conversion

    You can get some HDMI examples from here: **broken link removed**
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    1PPS Generator Module

    1. Go to SRS's website 2. Products -> Time & Frequency Instruments 3. Frequency Standards/Oscillators -> PRS10 10 MHz Rubidium Oscillator Ir is really easy.
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    1PPS Generator Module

    For example SRS FS725 Rubidium Frequency Standard
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    Is this old design a candidate for CPLD?

    You can do a simulation before you buy anything. Get Intel/Altera Quartus Prime (it's for free), you can build a logic circuit using block diagram a 74-family "virtual chips" and then compile it for different CPLDs and see if your design will fit into chips. You can start from Altera EPM3064 but...
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    Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    Ok, I see. Now this is oblivious for me why LEON3 soft-processor from grlib is using technology specific pads for every port from top level entity.
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    Briey SoC (RISCV) and Mimas V.2 Numato FPGA board

    But this functionality must be handled by SDRAM memory controller -- and after synthesis a proper bi-dir macro should be placed.
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    [SOLVED] RGMII problem with MAX 10 Development board

    Try using SignalTap logic analyzer to see if you can receive something. And the 88E1111 chip is hard to use because there is no public documentation for it. You have to pay and sign NDA to get any information about config. registers etc.
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    FPGA vendors outside USA

    There is one European FPGA manufacturer of the rad-hard chips: https://www.esa.int/Our_Activities/Space_Engineering_Technology/Shaping_the_Future/High_Density_European_Rad-Hard_SRAM-Based_FPGA-_First_Validated_Prototypes_BRAVE They plan to make a rad-hard SoC (ARM+FPGA) chips as well.
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    How to begin development on SOC (xilinx)

    You could also look at Cora Z7 board from Digilent - it's $99 and some pins are accessible over Pmod and Arduino like sheilds. The hardware itself is important but also docs provided by the pcb manufacturer and some examples might be useful as well.

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