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hi everybody,
I used to write vhdl code in ISE, but I was wondering is there any way to code for FPGA in some other languages or is there any converter that we could convert code from java or python to vhdl? I saw some converters but the converted code wasn't optimized.
I really appreciate if...
hi
i have some matlab code and i want to write matlab tesbench for them for using in hdl coder. I was wonder if is there any program for doing this like ISE Xillinx for vhdl??
thanks
I want to use the components value inside my code,I found that the process gets component value in next clk.how can i fix that??I mean if i want the value of one component,the value calculated and used immediately in the same clock
thank you!
u1 : f1 port map (y, x ,a , clk);
signal a ...
i know u said it before and i thank u,but this code is totally different.i wrote it just for simulation for a homework.
yes i remember u said to me before that i should write codes according to schematic,i wanted to learn it for my own but the codes that i posted before was just for simulation...
thanks for answering,
every time i ask a question u keep saying i dont understand hdl coding,but i think i should mention that i am a beginner and i am trying to learn it.
and every time a person ask a question it means that someone have problem in this part and it doesnt necessery means that he...
hi
i have the following code,that i use component inside it.but have the same errors and warnings for each line of component,i dont understand the errors.
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
--use ieee.std_logic_arith.all; --package needed for signed
--use IEEE.NUMERIC_STD.all;
use...
hi heres my code and the value o fignal is calculated correctly but at the ninth clk when the calculation finished ,out put should get the value but it didnt happen?
how could i fix it??
tnx
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all...
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