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Dear zxasqw123,
Of course the linearity of the front-end S/H stage is very important, since it directly affects the linearity of the input signal to the ADC. However, if the well-known Flip-Around structure is utilized as the S/H, the unity gain is almost independent of the capacitor mismatch...
Dear nooby,
The most important control factors for numbering formats in the printout/measurement listing are as follows:
- The .OPTION INGOLD controls the format of numbers in printouts.
- The .OPTION NUMDGT=x controls the listing printout accuracy.
- The .OPTION MEASDGT=x controls the measure...
Dear 020170,
You should add the keyword "sweep" before you determine the Monte Carlo iteration numbers. (like this:)
.tran 1u 230u sweep monte=10
Regards,
EZT
Re: PS,PD of a mosfet
Dear leohart,
"Since there is no field-implant along that edge, the sidewall capacitance is therefore smaller there". These are almost the exact words in Johns&Martin book. Well, I think there may still exist some small parasitic cap. due to fringing or some other...
Re: PS,PD of a mosfet
Dear leohart,
I guess the relation in the attached picture is correct, since one side of the Source/Drain junction is faced to the active channel and hence there exists no field-implant on that edge to result in the expected parasitic cap (or the parasitic cap would be...
Re: dynamic logic
Hi engrbabarmansoor,
As far as I know, it's first advantage is less number of transistors which results in less area or higher density in the same area compared to conventional static CMOS logic. BTW, the dynamic logic is actually an improved version of conventional ratioed...
Re: Please explain difference between these two 2stag op-amp
Hi yonzzan,
A switched-capacitor level-shifter is utilized in first cicuit in order to use nMOS transistor as the input devices of both stages (Since there are two pMOS trs. and three nMOS trs. stacked in the first stage, the output...
Re: -Vsb on an n-MOST
Dear dkace
I'm not sure if we are talking about the same region of operation!
If -|2ΦF|<Vsb<0 then the value of (|2ΦF|+Vsb) would be positive while Vsb is negative and square root is valid so those previous relations are correct in this interval. But if Vsb<-|2ΦF| then...
Re: -Vsb on an n-MOST
Hi dkace
With these conditions you described, there is no difference in usual I-V equations, except that Vth should be changed with its new value (threshold voltage would be less than Vt0, i.e., the threshold voltage when vsb=0).
Vth = Vt0 +...
Hi apmrao
As far as I know there is no exact relation between harmonic distortion and DC gain. Because harmonic distortion depends on several parameters. However as wonbef said, usually more DC-gain results in less harmonic distortion. Theoretically, one can express hamonic distortion factors by...
Re: how we can test the settling time of fully differential
Hi wael_wael
As you know, the settling time of any system is defind as the time it takes to reach its final value with a specified error (ess) after giving a step signal to the input. For an opamp there are two types of settling...
Re: Ramping Vdd
Hi.
You may use "pwl" (piece-wise linear) source (or vpwl instance in some simulators, i.e. pwl voltage source) to create any arbitrary signal. However in your case you can just use a "pulse" voltage source (vpulse instance in some simulators). For example in HSPICE:
.param...
Dear srikanth,
Area and perimeter of drain/source have a great dependency upon your utilized process/technology and the way you are going to lay it out (e.g. to the number of fingers). However in most simulators you can find the default values of these specifications for your device by using the...
Dear secret,
As you know for a device in deep-triode region:
Ron = L/(uCoxW(Vgs-Vth))
So to have a smaller on-resistance, you should utilize devices with minimum possible length and maximum width. However, by applying a higher Vgs(gate-source voltage) to your device you can decrease its...
Dear EMfox,
I think your problem is due to lack of body contact near a laid out device. In NMOS for example, after you add the NMOS instance (from a certain library) with required width and length, you should add an M1-to-SUB contact and put it beside the NMOS. Only in this case your 4-terminal...
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