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Recent content by extraord

  1. E

    How to use PSS analysis in Spectre?

    Re: PSS analysys your can find the tutorial in www.designers-guide.org or google for it.
  2. E

    BJT ESD failure, anyone has experience with that?

    from your decription the transistor doesn't look dead. I think this may caused by some parasitic devices which leakage the other 250uA.
  3. E

    need help on regulator

    I only have a 5v supply , and I need generate the 3.3v supply to drive the the digital cicuit working at the frequency 100k, the max current is 5mA for all the Precess , temp(-40~125), volatage(4.5~5.5). I need the 3.3v output varies within 10%. the question is: I have to use a 130nm TSMC...
  4. E

    the charge pump source follower

    but is this will affect the determistic jitter? is op's bandwidth is low
  5. E

    the charge pump source follower

    hi guys, recently I meet a very big issue. when I design the charge pump in PLL, usually we need a source follower to reduce the current mismatch. And people often design the bandwidth of OP over PFD frequency. But at this time we can not make it. So what I want to know is whether the...
  6. E

    a high resolution low offset comparator

    thanks for your help. I know the Av=3mV*1u. one more thing I want to know is how much difference of offset between your estimation and test results? or your simulation in monte carlo and test results.
  7. E

    a high resolution low offset comparator

    hi folks, recently I'm designing a circuit which need a very accurate comparator. the resolution must be smaller than 1mv. also the offset has to be less than 2-3mv(3 sigma). the process is tsmc13 logic. the area of it should be within 30umx30um speed is not very critical, 30ns for...
  8. E

    what's the trend of vth when width or length goes smaller?

    Re: what's the trend of vth when width or length goes smalle yes, I use hspice to check that. and almost all process include tsmc 13 18, behave like that. And vds=0. vg=0 or vdd the trend is almost the same. I think the ldd effects is one factor of that. but what's the meaning of FOX effects...
  9. E

    what's the trend of vth when width or length goes smaller?

    hi guys, I'm so confused that when i sweep the width or length of transistors and probe the vth of them. the trendency is when length goes smaller vth goes high. and when width goes larger vth goes high. all of these is directly different from text book. why?
  10. E

    how can i measure the power of input differential signal?

    Re: how can i measure the power of input differential signal i mean in real circuit.not simulation
  11. E

    how can i measure the power of input differential signal?

    in order to filter out the noise
  12. E

    which one is more matching for these two layouts?

    the source and drain are not the same, in modern process. the foundary usually do LDD in source and drain, so the plasma is not absolut vertical. although they shift the wafer around to make the source and drain doping similar, they are still different.
  13. E

    which one is more matching for these two layouts?

    in deep submicro <0.18um first is much better, absolutly
  14. E

    problem on using cadence stability(stb) analysis

    analyste stb cadence you can use ac analysis , and use big LC to break the loop at high frequency.
  15. E

    How to design the channel length of transistors in this SA?

    Re: sense amplifier design sense amplifier do not need high gain, so high speed is the critical
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