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Hi,
It is not from a layout, only a simple SPICE file. Here is the output waveform
The red one is input B and the other is the output. As you can see from the measurement, the X value in output waveform is smaller than X value in the input waveform. The value of Y is 1.65 (VDD/2)
The width...
Hi Keith,
Thanks for response. I measure it using the statements below
.TRAN 0.01ns 100ns
* Measure delay from input B to output OUT
.MEASURE TRAN tPHL TRIG V(B) VAL=1.65 RISE=3 TARG V(OUT) VAL=1.65 FALL=3
.MEASURE TRAN tPLH TRIG V(B) VAL=1.65 FALL=3 TARG V(OUT) VAL=1.65 RISE=3
.MEASURE TRAN...
Hi,
I'm doing a simulation of a CMOS NOR gate using hspice and
want measure tplh and tphl from input A to the output. The input signal to A is a pulse waveform swing from 0 to 3.3V, input B is 0V. It seems ok and work fine. I can get the tplh and tphl
The problem is when the condition is...
Hi,
I'm doing a simulation of a CMOS NOR gate using hspice and
want measure tplh and tphl from input A to the output. The input signal to A is a pulse waveform swing from 0 to 3.3V, input B is 0V. It seems ok and work fine. I can get the tplh and tphl
The problem is when the condition is...
Hi all,
I want to implement a simple DFA on FPGA using Verilog or VHDL. I read from some papers that the states of the DFA and the state transition table can be stored in BRAM. Anybody here can give me a hint how to do this? Thank you.
fpga hash function
Hi all,
I'm trying to implement hash function. This hash function hashes 32-bit number. Which hash functions are suitable for FPGA implementation? H3, Jenkins, FNV, Murmur? Any suggestions and examples? Thank you
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