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Hi all,
I am doing gate level simulation and find there are Xs in my circuit. For example, I have output port out_A = 'X'. Does this simulator have capability to trace to the source 'X' ?
Thanks.
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escape from overcharge during manufacturing, overcharge could break down the gate, causing permernant failure. Gate oxide integrity means no such failure.
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Re: Hierarchy or Flatten
Of coz you should use flatten mode whenever possible but guess how to cope with 5M instance design??? After a single command, you'll have to wait for 10 hours...
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have u read manpage or help of write_delay_paths? I doubt your usage is not very proper. -slack may help.
Added after 7 minutes:
Extracting Slack Data from PrimeTime
TetraMAX utilizes a specific set of timing data extracted from PrimeTime. To obtain this
information, you need to call a...
Once again, synthesis has nothing to do with memory initialization.
Just complie them. In your testbench, use readmemb to initialize your memory values with hierarchical names...
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