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Hello!
I get a Verilog netlist after synthesis and convert it Spice netlist by nettran, I want use this Spice netlist inputting Nanosim for simulation.
But some problems in the Spice netlist:
1. The Verilog netlist hasn't power and ground connections, so in the Spice netlist also missing the...
Hello!
I use write_lib command in Synthesis 2010 covert lib file to db file then input in Astro 2007, it's error input.
Then I use Synthesis 2007 covert the same lib file to db file, the Astro 2007 can recognize this file.
And the db files size are different, the 2007 version is bigger than...
Hello!
I am running NCX tool making 0.18um 5V digital standard cells .lib file.
When I writing the .indices file that needed when running the tool. Some index values must be setup before running:
ncx_input_net_transition_index : 0.03, 0.1, 0.4, 0.9, 1.5, 2.2, 3 ...
The power start sequence been showed in PIC, how can I protect my chip if the sequence run mistake?
Like the PIC show, the sequence is VCC-VEE-VGG when the power up and reversed when the power down, I want insure that when the sequence wrong, the chip don't work. How can I design the internal...
I'm designing a level shifter to convert 0~5v digital voltage to -15~25v. I know a four mos circuit can accomplish it.
1.That circuit must convert 0~5v to 0~25v, then convert it to -15~25v. Does it a circuit convert the voltage directly?
2.I add two mos to decrease the current when the voltage...
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