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Recent content by Elephantus

  1. E

    AUTOOUT problems with Cypress EZ-USB FX2

    outpktend Hi all. I am interfacing the Cypress EZ-USB FX2LP (Cy7C68013A) to a Lattice FPGA. The data is transferred from PC in AUTOOUT mode (auto-commit to peripheral domain) and the data is read from the USB chip through the slave FIFO interface. Endpoint 2 is used, the fifo uses double...
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    GSR on lattice ECP2 device

    lattice gsr Hi all. I am debugging a design on Lattice ECP2 device, and during the PAR phase the ISPlever software generates a message similar to: "Using <design net> as GSR". Now, it is a bit odd to have a signal that should also be reset by GSR in the start, and which is actually a...
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    Assigning more than one task to a state (in WITH statement)

    Re: Assigning more than one task to a state (in WITH stateme Hi. As per discussion in the other thread(If- Then VHDL error), there is an alternative way of doing this. architecture RTL of mycode is type state_type is (I0,I1,I2,I3,I4,I5,I6); signal curr_state,next_state : state_type...
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    Why I have If-then VHDL errors in my code?

    if condition in vhdl Correct. You can describe combinatorial logic without using a process. But you cannot use if.. then.. else constructs outside of a process. Writing the code -- 3 State types if (m = LOAD) then t <= T1; elsif (m = MOV or m = NEG) then t <= T2; else...
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    Why I have If-then VHDL errors in my code?

    error (10500): vhdl Hi. In this process, m is not a clock. Synchronous (clocked) logic is described in a different manner in VHDL. When you define a process: process(a,b,c) is begin if c = '0' then d <= a xor b; else d <= b xor c; end if; end process; The signals in...
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    Why I have If-then VHDL errors in my code?

    if else vhdl Hi. The code: -- 3 State types if (m = LOAD) then t <= T1; elsif (m = MOV or m = NEG) then t <= T2; else t <= T3; end if; Is a sequential statement, not a concurrent one, and cannot be written outside a process begin/end block. Therefore, you...
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    Who is Market Leader in FPGA - ALTERA or XILINX

    What is the situation with the market share of other vendors, namely Actel and Lattice?
  8. E

    Manual floorplanning of FPGA designs

    fpga floorplanning Can anyone suggest where to look for for resources and tutorials on manual FPGA design floorplanning, possibly for Xilinx chips? I would appreciate any help.
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    How to make an LFSR with a loop length of 5 or 10 clock cycles?

    Hi. Does anyone know the taps to make an LFSR with a loop length of 5 or 10 clock cycles? Thanks in advance.
  10. E

    USB to Paralle at HIGH SPEED

    Perhaps mass storage drivers exist for the FX2, but CyUSB.sys driver and its CyAPI enable direct control of transfers to individual USB endpoints on the chip from within the application software. See this ref design: https://www.cypress.com/design/RD1048
  11. E

    USB to Paralle at HIGH SPEED

    My choice would be the EZ-USB FX2 LP from Cypress. Part number is CY7C68013A. It comes with its own driver which has a very nice user mode API you can use from your code, and you practically get the firmware needed for high speed transfers with it. The embedded 8051 cpu can control the traffic...
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    Advanced constructs in VHDL for synthesis

    vhdl fileio Hi all. I was looking through multiple IP cores recently and I noticed that most of the cores use a very limited subset of VHDL. However, looking at synthesis tools available today, I noticed that they support quite a lot of language features including structured datatypes...
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    Question about using dual port BRAM with Spartan-II

    Re: BRAM Spartan-II The PCI core therefore expects to have the data ready when the ENA signal which it produces is high, to sample it on the next rising edge of clock? This seems highly unusual for a synchronous design. If it is absolutely necessary, you could either try inverting the port A...
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    Question about using dual port BRAM with Spartan-II

    Re: BRAM Spartan-II Hi. If you are using RAMB4_S16 blockram from spartan II, you apparently cannot have the output in the same clock cycle the write enable strobe is asserted as the BRAM has a synchronous write, the ENA will get sampled on the next rising edge of clock. Also, why do you need...
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    DDR sampling of LVDS inputs on Xilinx Spartan-3

    xilinx ibufds ddr Hi all. I am working on implementing an LVDS interface on a Xilinx Spartan-3 chip, and I want to do DDR sampling of input data. The first idea was to directly instantiate the IBUFDS primitive for external LVDS interface, and then connect the output of IBUFDS to IFDDRCPE DDR...
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