Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Why Parasitic Inductance of Cadence Capacitor Varies Very Little with Its Size
After dealing quite a lot with the parasitics of inductors and capacitors, I'm wondering why the parasitic inductance of a capacitor seems almost independent of its size? I'm simulating rfmimcap capacitors in...
I'm using this formula fmax=rad((fT.n.L)/(8.pi.Rs.W.Cgd)) to calculate the fmax of an rfnmos2v transistor in Cadence, where fT=gm/2.pi.Cgg, n=number of fingers, Rs=sheet resistance, and Cgd=0.4f.W(in mircometers). W and L are clearly the width and length of per finger, and I'm using 180nm...
I'm looking for a creditable formula to calculate the gate-drain capacitance of a MOSFET. I've found a few equations online, but they are either too trivial (for example, Cgd=WCov) or too complicated (Cgd=Cgd,setup+WCgd,f+WLeffCgd,in). The first one doesn't seem to give very exact results, and...
Well... Still,the EM simulations give an inductance with a maximum variation of 10pH from the Cadence result, and it's something in the formula that seems wrong.
Thank you so much, volker! Here's the problem: I have an 180nm CMOS inductor in Cadence with an inner radius of r=30u, a width of w=6u, and spacing of s=2u, with one turn. Cadence shows an inductance of L=307.91pH for it, while Rosa's formula yields 142.9pH, Wheeler's 141.14pH, and monomial...
I know it's a tedious process, and may not even make sense when there are EM simulators and software like ASITIC designed particularly for this. But I kind of have to do it. I'm taking the resistive and capacitive parasitics of the metal traces and the substrate,and the metal oxide substrate...
I've been calculating the inductance of a 0.18u CMOS process inductor in Cadence using several formulas such as Wheeler's, Rosa's and monomial expressions for octagonal spiral inductors. All these formulas give the same amount with very little variation while the real inductance is significantly...
I'm new to HFSS, and I want to EM simulate the ind_std model in Cadence Virtuso using it. I've imported the .gds file and set up a driven modal solution type, but I'm confused about assigning boundaries and excitations. I have already desgined an inductor from scratch using tutorials I've found...
Thank you very much, volker@muehlhaus. The information was helpful, though I've found a seemingly more complete model with all the values in the book "RF Power Amplifiers" by Dr.M. Kazimierczuk. The results it yields are close enough to my estimations, so I guess it can help me work something...
Thank you for your reply. Yes, I know how to measure the DC resistance and all, and I've got estimations of all parasitic elements, but I'm looking for an exact calculational base for my measurements.
I've come across a model whose image I've uploaded, and I've found all the parameters in it...
I am trying to provide an algorithm to design a distributed amplifier at 40GHz based on mere calculation for which I need to model the elements of my artificial transmission line as precisely as possible. I've found simple models to calculate the parasitic resistance and inductance of a...
I'm designing a distributed amplifier circuit in the Ka band, and I'm wondering whether AC analysis yields reliable results for this frequency or not? I'm observing my results using PAC, SP and AC analysis, the answer AC gives is consistent with my design calculations, but both SP and PAC give...
It is stated in several papers that if you design a DA using high-pass transmission lines, the DA would most probably act as a band-pass amplifier as the line losses degrade performance in high frequencies and decrease the gain.
I have designed a BPDA based on this concept, and I'm facing a...
Yes, that's exactly right. But I'm looking for a more specific merit to help me judge which is better at my band. I'm currently in the cadence spectre design stage, and I don't know how much chip area I need yet. I've seen papers designing the DA with inductors in the mentioned band, and I've...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
