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Gopal,
use nay genric 0.18 model. they will work with SCL.
Symica : No layout possible with DRC /LVS free layout tools not available.
Simulation : free 300 nodes max, bias info (i, V) incomplete . level 49 models will work. simulation OK.
Graph : Average , calculator function limited.
SCl...
if are going to spend money to fabricate a chip that will work then go for Cadence Spectre , otherwise any tool would be good. Tanner tools are baby tools. their LVS /Extraction / net-list import is rubbish. The T-Spice is accurate simulator comparable with spectre /Hspice. other tools will be...
Smaller area device will be fast , but is it lacks drive. there is a optimal point were drive and area meet the basic requirement. designer adjust for higher width to get drive at the cost of power.
the best way to get min devices for synthesis is
1. Use Synopysis tools.
2. Use gates with lower...
There are two versions see, gEdA on google. One is direct copy and use other comes with a makefile that you can compile and use. ( I prefer make file method it gives less problems later) the development on this tool is now stopped. May be its time some Indian groups keep it alive.
Assura is junk tool and has its mood . you could do one thing remove assura working dir in your design, remove all hidden files .assura in your login account, and try to run assura ( cadence calls it cleanup , !) may be helps
SEE THE SITE: Experimental Physics with Phoenix and Python LG #111 HOPE IT HELPS . You may write to Dr Ajit kumar, NSC delhi who is spearheading the Linux hardware for teaching .
Don't go for latest spec.. but ram mem should be least 1GB buy a laptop where RHEL 4.8 will work. on this version as on today all EDA tools work good . see that windows Xp can be loaded well. other OS have issues.
only cadence can tell you exact level mapping quickly , you may use HSpice in cadence and by pass the problem . even in cadence orcad bsim3 is level 7 and in cadence spectre its level 49/53 !
What you expect is right to some extent of frequency. your freq of 12G is very high may be there is gain peaking at some point . It would be better to see integrated rms noise plot vs frequency it will provide better insight. Without actual circuit or ac gain plot it difficult to pinpoint.
In AMS in library setting provide the path of model. in the schematic edit the CDF parameter for model name. done ! CDF parameter can be changed form ICFB menu also.
The synthesis tool inserts logic cell to meet the timing and reduce slag/skew. doing so it may have to add more cell to balance load, so again some cells are added. therefore the cells increase. High performance cells are handcrafted at schematic level and layout made by direct silicon layout...
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