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Recent content by EEsj

  1. E

    Using "circuit conditions" in SPECTRE

    In analog we typically DC bias all transistors to be at the edge of triode/linear region. If I am to use the circuit condition tool in spectre should I expect all transistors to be highlighted? a simple example is a diode connected pair (who is always saturated) will appear highlighted.
  2. E

    Corners versus Monte Carlo?

    Corners and Monte Carlo both run simulations versus PVT. Which simulation is better characterizes a circuit's robustness?
  3. E

    How to setup a corners simulation?

    Hi, Does anyone have a tutorial on how to setup a corners simulation?
  4. E

    gummel poon model vs HICUM model

    Hi I am looking at a modeling design manual for a SiGe process and am sort of unsure of which HBT model to use. When i run PVT monte carlo the simulator defaults to gummel poon model for the simulation, but the manual states that HICUM may be more accurate. data shown in the manual show...
  5. E

    Are there some GaAs ADC products?

    I highly doubt it...the only GaAs components (other than RF) that i have used are things like d-flip flops and ECL logic chips. You can check out On-Semi since the still fab the old Motorola MCL parts.
  6. E

    Assura RCX, simulator fails to extract the PDK

    Hi I am using a PDK and used caps and inductors from the design kit. When I run Rcx to generate an RC av_extracted view the simulator fails to extract the PDK caps and inductors. I do not get any errors ie extraction succeeds, so I am not to sure where the problem is. any help is...
  7. E

    NWELL under bump pad layout??? help!!

    Hi I am trying to layout a bump pad. my layers (assume following DR) look like this bump pad marking layer top_metal layer nwell (floating) this does not give me any DRC errors which is what i expect. When i incorporte this bump pad in my overall layout I recieve an nwell stamp error. The...
  8. E

    ground up IC Layout book???

    Hi Can anyone recommend a book or tutorial that guides someone on all the necessary components for an IC layout? One must learn from experience but some "template" must exist to act as a minimum standard. Any help is greatly appreciated!
  9. E

    why FM tx distance is small?

    have you monitored the spectrum on an analyzer? Have you swept the output impedance smith chart and antenna impedance? You're probably not tuned correctly and not delivering enough power to the antenna to complete the link.
  10. E

    using ADS momentum S-parameter data in Cadence Virtuoso ?

    Hi can anyone point me to a tutorial on how I can use S-parameter data from Momentum (for example and inductor) in Cadence? Thanks!
  11. E

    Looking for gpdk090 pcells for Cadence

    hi does anyone have pcells for gpdk090 for cadence?
  12. E

    single testbench to find gm*rds

    it probably is simple....but i just cant see it... I need to be able to sweep the two voltages and extract both Ids Vgs and Ids Vds.. so im still thinking.
  13. E

    How to simulate RDS of a PowerMOSFET?

    take the IV vs VDS curve...ie sweep VDS then take the inverse of the derivative of the current
  14. E

    Need Comment from Designer: Why Flicker Noise is Critical?

    Re: Need Comment from Designer: Why Flicker Noise is Critica 1/f noise is very critical in RF or Analog circuits since the with large swing behavior the MOS is experiencing nonlinear gain beahavior... therefore even though 1/f noise seems to dissapear at higher frequencies...this low freq noise...
  15. E

    single testbench to find gm*rds

    does anyone know a single test bench that will allow me to calculate gm*rds for an nmos? ie be able to simultaneously get IdVsVgs and Id Vs Vds curves

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